simple_v_extension/sv_prefix_proposal.rst

   1 SimpleV Prefix (SVprefix) Proposal v0.3
   2 =======================================
   3
   4 This proposal is designed to be able to operate without SVorig, but not to
   5 require the absence of SVorig See Specification_.
   6
   7 .. _Specification: http://libre-riscv.org/simple_v_extension/specification/
   8
   9 .. contents::
  10
  11 Conventions
  12 ===========
  13
  14 Conventions used in this document:
  15 - Bits are numbered starting from 0 at the LSB, so bit 3 is 1 in the integer 8.
  16 - Bit ranges are inclusive on both ends, so 5:3 means bits 5, 4, and 3.
  17
  18 Operations work on variable-length vectors of sub-vectors, where each sub-vector
  19 has a length *svlen*, and an element type *etype*. When the vectors are stored
  20 in registers, all elements are packed so that there is no padding in-between
  21 elements of the same vector. The number of bytes in a sub-vector, *svsz*, is the
  22 product of *svlen* and the element size in bytes.
  23
  24 Options
  25 =======
  26
  27 * SVPrefix augments the main Specification_
  28 * SVPregix operates independently, without the VL (and MVL) CSRs (in any priv level)
  29 * SVPrefix operates independently, without the SUBVL CSRs (in any priv level)
  30 * SVPrefix operates independently, with no support for VL (or MVL) overrides in the 64 bit instruction format either (VLtyp=0)
  31 * SVPrefix operates independently, with no support for svlen (SUBVL) overrides in either the 48 or 64 bit instruction format either (svlen=0).
  32
  33 All permutations of the above options are permitted, and in the UNIX platform must raise illegal instruction exceptions on implementations that do not support them.
  34
  35 The options
  36
  37 If required, the STATE, VL, MVL and SUBVL CSRs all operate according to the main specification: hypothetically an implementor could choose not to support setting of VL, MVL or SUBVL (only allowing them to be set to a value of 1). STATE would then not be required either.
  38
  39 If support for SUBVL is to be provided, storing of the sub-vector offsets and SUBVL itself (and context switching of the same) in the STATE CSRs are mandatory.
  40
  41 If support for VL is to be provided, storing of VL, MVL and the dest and src offsets (and context switching of the same) in the STATE CSRs are mandatory.
  42
  43 Half-Precision Floating Point (FP16)
  44 ====================================
  45
  46 If the F extension is supported, SVprefix adds support for FP16 in the
  47 base FP instructions by using 10 (H) in the floating-point format field *fmt*
  48 and using 001 (H) in the floating-point load/store *width* field.
  49
  50 Compressed Instructions
  51 =======================
  52 This proposal does not include any prefixed RVC instructions, instead, it will
  53 include 32-bit instructions that are compressed forms of SVprefix 48-bit
  54 instructions, in the same manner that RVC instructions are compressed forms of
  55 RVI instructions. The compressed instructions will be defined later by
  56 considering which 48-bit instructions are the most common.
  57
  58 48-bit Prefixed Instructions
  59 ============================
  60 All 48-bit prefixed instructions contain a 32-bit "base" instruction as the
  61 last 4 bytes. Since all 32-bit instructions have bits 1:0 set to 11, those bits
  62 are reused for additional encoding space in the 48-bit instructions.
  63
  64 64-bit Prefixed Instructions
  65 ============================
  66
  67 The 48 bit format is further extended with the full 128-bit range on all source
  68 and destination registers, and the option to set both VL and MVL is provided.
  69
  70 48-bit Instruction Encodings
  71 ============================
  72
  73 In the following table, *Reserved* entries must be zero.  RV32 equivalent encodings
  74 included for side-by-side comparison (and listed below, separately).
  75
  76 First, bits 17:0:
  77
  78 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  79 | Encoding      | 17     | 16         | 15         | 14  | 13         | 12          | 11:7 | 6          | 5:0    |
  80 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  81 | P48-LD-type   | rd[5]  | rs1[5]     | vitp7[6]   | vd  | vs1        | vitp7[5:0]         | *Reserved* | 011111 |
  82 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  83 | P48-ST-type   |vitp7[6]| rs1[5]     | rs2[5]     | vs2 | vs1        | vitp7[5:0]         | *Reserved* | 011111 |
  84 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  85 | P48-R-type    | rd[5]  | rs1[5]     | rs2[5]     | vs2 | vs1        | vitp6              | *Reserved* | 011111 |
  86 +---------------+--------+------------+------------+-----+------------+--------------------+------------+--------+
  87 | P48-I-type    | rd[5]  | rs1[5]     | vitp7[6]   | vd  | vs1        | vitp7[5:0]         | *Reserved* | 011111 |
  88 +---------------+--------+------------+------------+-----+------------+--------------------+------------+--------+
  89 | P48-U-type    | rd[5]  | *Reserved* | *Reserved* | vd  | *Reserved* | vitp6              | *Reserved* | 011111 |
  90 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  91 | P48-FR-type   | rd[5]  | rs1[5]     | rs2[5]     | vs2 | vs1        | *Reserved*  | vtp5 | *Reserved* | 011111 |
  92 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  93 | P48-FI-type   | rd[5]  | rs1[5]     | vitp7[6]   | vd  | vs1        | vitp7[5:0]         | *Reserved* | 011111 |
  94 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  95 | P48-FR4-type  | rd[5]  | rs1[5]     | rs2[5]     | vs2 | rs3[5]     | vs3 [#fr4]_ | vtp5 | *Reserved* | 011111 |
  96 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  97
  98 .. [#fr4] Only vs2 and vs3 are included in the P48-FR4-type encoding because
  99           there is not enough space for vs1 as well, and because it is more
 100           useful to have a scalar argument for each of the multiplication and
 101           addition portions of fmadd than to have two scalars on the
 102           multiplication portion.
 103
 104 Table showing correspondance between P48-*-type and RV32-*-type.  These are
 105 bits 47:18 (RV32 shifted up by 16 bits):
 106
 107 +---------------+---------------+
 108 | Encoding      | 47:18         |
 109 +---------------+---------------+
 110 | RV32 Encoding | 31:2          |
 111 +---------------+---------------+
 112 | P48-LD-type   | RV32-I-type   |
 113 +---------------+---------------+
 114 | P48-ST-type   | RV32-S-Type   |
 115 +---------------+---------------+
 116 | P48-R-type    | RV32-R-Type   |
 117 +---------------+---------------+
 118 | P48-I-type    | RV32-I-Type   |
 119 +---------------+---------------+
 120 | P48-U-type    | RV32-U-Type   |
 121 +---------------+---------------+
 122 | P48-FR-type   | RV32-FR-Type  |
 123 +---------------+---------------+
 124 | P48-FI-type   | RV32-I-Type   |
 125 +---------------+---------------+
 126 | P48-FR4-type  | RV32-FR-type  |
 127 +---------------+---------------+
 128
 129 Table showing Standard RV32 encodings:
 130
 131 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 132 | Encoding      | 31:27       | 26:25 | 24:20    | 19:15    | 14:12  | 11:7     | 6:2    | 1      | 0          |
 133 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 134 | RV32-R-type   +    funct7           + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0]  + opcode + 1      + 1          |
 135 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 136 | RV32-S-type   + imm[11:5]           + rs2[4:0] + rs1[4:0] + funct3 | imm[4:0] + opcode + 1      + 1          |
 137 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 138 | RV32-I-type   + imm[11:0]                      + rs1[4:0] + funct3 | rd[4:0]  + opcode + 1      + 1          |
 139 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 140 | RV32-U-type   + imm[31:12]                                         | rd[4:0]  + opcode + 1      + 1          |
 141 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 142 | RV32-FR4-type + rs3[4:0]    + fmt   + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0]  + opcode + 1      + 1          |
 143 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 144 | RV32-FR-type  + funct5      + fmt   + rs2[4:0] + rs1[4:0] + rm     | rd[4:0]  + opcode + 1      + 1          |
 145 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 146
 147 64-bit Instruction Encodings
 148 ============================
 149
 150 Where in the 48 bit format the prefix is "0b0011111" in bits 0 to 6, this is
 151 now set to "0b0111111".
 152
 153 +---------------+---------------+--------------+-----------+
 154 | 63:48         | 47:18         | 17:7         | 6:0       |
 155 +---------------+---------------+--------------+-----------+
 156 | 64 bit prefix | RV32[31:3]    | P48[17:7]    | 0b0111111 |
 157 +---------------+---------------+--------------+-----------+
 158
 159 * The 64 bit prefix format is below
 160 * Bits 18 to 47 contain bits 3 to 31 of a standard RV32 format
 161 * Bits 7 to 17 contain bits 7 through 17 of the P48 format
 162 * Bits 0 to 6 contain the standard RV 64-bit prefix 0b0111111
 163
 164 64 bit prefix format:
 165
 166 +--------------+-------+--------+--------+--------+--------+
 167 | Encoding     | 63    | 62     | 61     | 60     | 59:48  |
 168 +--------------+-------+--------+--------+--------+--------+
 169 | P64-LD-type  | rd[6] | rs1[6] |        |        | VLtyp  |
 170 +--------------+-------+--------+--------+--------+--------+
 171 | P64-ST-type  |       | rs1[6] | rs2[6] |        | VLtyp  |
 172 +--------------+-------+--------+--------+--------+--------+
 173 | P64-R-type   | rd[6] | rs1[6] | rs2[6] |        | VLtyp  |
 174 +--------------+-------+--------+--------+--------+--------+
 175 | P64-I-type   | rd[6] | rs1[6] |        |        | VLtyp  |
 176 +--------------+-------+--------+--------+--------+--------+
 177 | P64-U-type   | rd[6] |        |        |        | VLtyp  |
 178 +--------------+-------+--------+--------+--------+--------+
 179 | P64-FR-type  |       | rs1[6] | rs2[6] |        | VLtyp  |
 180 +--------------+-------+--------+--------+--------+--------+
 181 | P64-FI-type  | rd[6] | rs1[6] | rs2[6] |        | VLtyp  |
 182 +--------------+-------+--------+--------+--------+--------+
 183 | P64-FR4-type | rd[6] | rs1[6] | rs2[6] | rs3[6] | VLtyp  |
 184 +--------------+-------+--------+--------+--------+--------+
 185
 186 The extra bit for src and dest registers provides the full range of
 187 up to 128 registers, when combined with the extra bit from the 48 bit
 188 prefix as well.  VLtyp encodes how (whether) to set VL and MAXVL.
 189
 190 VLtyp field encoding
 191 ====================
 192
 193 +-----------+-------------+--------------+----------+----------------------+
 194 | VLtyp[11] | VLtyp[10:6] | VLtyp[5:1]   | VLtyp[0] | comment              |
 195 +-----------+-------------+--------------+----------+----------------------+
 196 | 0         |  000000     | 00000        |  0       | no change to VL/MVL  |
 197 +-----------+-------------+--------------+----------+----------------------+
 198 | 0         |  VLdest     | VLEN         |  vlt     | VL imm/reg mode (vlt)|
 199 +-----------+-------------+--------------+----------+----------------------+
 200 | 1         |  VLdest     | MVL+VL-immed | 0        | MVL+VL immed mode    |
 201 +-----------+-------------+--------------+----------+----------------------+
 202 | 1         |  VLdest     |  MVL-immed   | 1        | MVL immed mode       |
 203 +-----------+-------------+--------------+----------+----------------------+
 204
 205 Note: when VLtyp is all zeros, neither VL nor MVL are changed.
 206
 207 Just as in the VLIW format, when bit 11 of VLtyp is zero:
 208
 209 * if vlt is zero, bits 1 to 5 specify the VLEN as a 5 bit immediate
 210   (offset by 1: 0b00000 represents VL=1, 0b00001 represents VL=2 etc.)
 211 * if vlt is 1, bits 1 to 5 specify the scalar (RV standard) register
 212   from which VL is set.  x0 is not permitted
 213 * VL goes into the scalar register VLdest (if VLdest is not x0)
 214
 215 When bit 11 of VLtype is 1:
 216
 217 * if VLtyp[0] is zero, both MAXVL and VL are set to (imm+1).  The same
 218   value goes into the scalar register VLdest (if VLdest is not x0)
 219 * if VLtyp[0] is 1, MAXVL is set to (imm+1).
 220   VL will be truncated to within the new range (if VL was greater
 221   than the new MAXVL).  The new VL goes into the scalar register VLdest
 222   (if VLdest is not x0).
 223
 224 This gives the option to set up VL in a "loop mode" (VLtype[11]=0) or
 225 in a "one-off" mode (VLtype[11]=1) which sets both MVL and VL to the
 226 same immediate value.  This may be most useful for one-off Vectorised
 227 operations such as LOAD-MULTI / STORE-MULTI, for saving and restoration
 228 of large batches of registers in context-switches or function calls.
 229
 230 vs#/vd Fields' Encoding
 231 =======================
 232
 233 +--------+----------+----------------------------------------------------------+
 234 | vs#/vd | Mnemonic | Meaning                                                  |
 235 +========+==========+==========================================================+
 236 | 0      | S        | the rs#/rd field specifies a scalar (single sub-vector); |
 237 |        |          | the rs#/rd field is zero-extended to get the actual      |
 238 |        |          | 7-bit register number                                    |
 239 +--------+----------+----------------------------------------------------------+
 240 | 1      | V        | the rs#/rd field specifies a vector; the rs#/rd field is |
 241 |        |          | decoded using the `Vector Register Number Encoding`_ to  |
 242 |        |          | get the actual 7-bit register number                     |
 243 +--------+----------+----------------------------------------------------------+
 244
 245 If a vs#/vd field is not present, it is as if it was present with a value that
 246 is the bitwise-or of all present vs#/vd fields.
 247
 248 * scalar register numbers do NOT increment when allocated in the
 249   hardware for-loop.  the same scalar register number is handed
 250   to every ALU.
 251
 252 * vector register numbers *DO* increase when allocated in the
 253   hardware for-loop.  sequentially-increasing register data
 254   is handed to sequential ALUs.
 255
 256 Vector Register Number Encoding
 257 ===============================
 258
 259 For the 48 bit format, when vs#/vd is 1, the actual 7-bit register number is derived from the
 260 corresponding 6-bit rs#/rd field:
 261
 262 +---------------------------------+
 263 | Actual 7-bit register number    |
 264 +===========+=============+=======+
 265 | Bit 6     | Bits 5:1    | Bit 0 |
 266 +-----------+-------------+-------+
 267 | rs#/rd[0] | rs#/rd[5:1] | 0     |
 268 +-----------+-------------+-------+
 269
 270 For the 64 bit format, the 7 bit register is constructed from the 7 bit fields: bits 0 to 4 from the 32 bit RV Standard format, bit 5 from the 48 bit prefix and bit 6 from the 64 bit prefix.  Thus in the 64 bit format the full range of up to 128 registers is directly available. This for both when either scalar or vector mode is set.
 271
 272 Load/Store Kind (lsk) Field Encoding
 273 ====================================
 274
 275 +--------+-----+--------------------------------------------------------------------------------+
 276 | vd/vs2 | vs1 | Meaning                                                                        |
 277 +========+=====+================================================================================+
 278 | 0      | 0   | srcbase is scalar, LD/ST is pure scalar.                                       |
 279 +--------+-----+--------------------------------------------------------------------------------+
 280 | 1      | 0   | srcbase is scalar, LD/ST is unit strided                                       |
 281 +--------+-----+--------------------------------------------------------------------------------+
 282 | 0      | 1   | srcbase is a vector (gather/scatter aka array of srcbases). VSPLAT and VSELECT |
 283 +--------+-----+--------------------------------------------------------------------------------+
 284 | 1      | 1   | srcbase is a vector, LD/ST is a full vector LD/ST.                             |
 285 +--------+-----+--------------------------------------------------------------------------------+
 286
 287 Notes:
 288
 289 * A register strided LD/ST would require *5* registers. srcbase, vd/vs2, predicate 1, predicate 2 and the stride register.
 290 * Complex strides may all be done with a general purpose vector of srcbases.
 291 * Twin predication may be used even when vd/vs1 is a scalar, to give VSPLAT and VSELECT, because the hardware loop ends on the first occurrence of a 1 in the predicate when a predicate is applied to a scalar.
 292 * Full vectorised gather/scatter is enabled when both registers are marked as vectorised, however unlike e.g Intel AVX512, twin predication can be applied.
 293
 294 Open question: RVV overloads the width field of LOAD-FP/STORE-FP using the bit 2 to indicate additional interpretation of the 11 bit immediate. Should this be considered?
 295
 296
 297 Sub-Vector Length (svlen) Field Encoding
 298 =======================================================
 299
 300 Bitwidth, from VL's perspective, is a multiple of the elwidth times svlen.  So within each loop of VL there are svlen sub-elements of elwidth in size, just like in a SIMD architecture. When svlen is set to 0b00 (indicating svlen=1) no such SIMD-like behaviour exists and the subvectoring is disabled.
 301
 302 Predicate bits do not apply to the individual sub-vector elements, they apply to the entire subvector group. This saves instructions on setup of the predicate.
 303
 304 +----------------+-------+
 305 | svlen Encoding | Value |
 306 +================+=======+
 307 | 00             | 1     |
 308 +----------------+-------+
 309 | 01             | 2     |
 310 +----------------+-------+
 311 | 10             | 3     |
 312 +----------------+-------+
 313 | 11             | 4     |
 314 +----------------+-------+
 315
 316 TODO : resolve interactions when SV VLIW Mode is active, as SVLEN is also a CSR.
 317
 318 Predication (pred) Field Encoding
 319 =================================
 320
 321 +------+------------+--------------------+----------------------------------------+
 322 | pred | Mnemonic   | Predicate Register | Meaning                                |
 323 +======+============+====================+========================================+
 324 | 000  | *None*     | *None*             | The instruction is unpredicated        |
 325 +------+------------+--------------------+----------------------------------------+
 326 | 001  | *Reserved* | *Reserved*         |                                        |
 327 +------+------------+--------------------+----------------------------------------+
 328 | 010  | !x9        | x9 (s1)            | execute vector op[0..i] on x9[i] == 0  |
 329 +------+------------+                    +----------------------------------------+
 330 | 011  | x9         |                    | execute vector op[0..i] on x9[i] == 1  |
 331 +------+------------+--------------------+----------------------------------------+
 332 | 100  | !x10       | x10 (a0)           | execute vector op[0..i] on x10[i] == 0 |
 333 +------+------------+                    +----------------------------------------+
 334 | 101  | x10        |                    | execute vector op[0..i] on x10[i] == 1 |
 335 +------+------------+--------------------+----------------------------------------+
 336 | 110  | !x11       | x11 (a1)           | execute vector op[0..i] on x11[i] == 0 |
 337 +------+------------+                    +----------------------------------------+
 338 | 111  | x11        |                    | execute vector op[0..i] on x11[i] == 1 |
 339 +------+------------+--------------------+----------------------------------------+
 340
 341 Twin-predication (tpred) Field Encoding
 342 =======================================
 343
 344 +-------+------------+--------------------+----------------------------------------------+
 345 | tpred | Mnemonic   | Predicate Register | Meaning                                      |
 346 +=======+============+====================+==============================================+
 347 | 000   | *None*     | *None*             | The instruction is unpredicated              |
 348 +-------+------------+--------------------+----------------------------------------------+
 349 | 001   | x9,off     | src=x9, dest=none  | src[0..i] uses x9[i], dest unpredicated      |
 350 +-------+------------+                    +----------------------------------------------+
 351 | 010   | off,x10    | src=none, dest=x10 | dest[0..i] uses x10[i], src unpredicated     |
 352 +-------+------------+                    +----------------------------------------------+
 353 | 011   | x9,10      | src=x9, dest=x10   | src[0..i] uses x9[i], dest[0..i] uses x10[i] |
 354 +-------+------------+--------------------+----------------------------------------------+
 355 | 100   | *None*     | *RESERVED*         | Instruction is unpredicated (TBD)            |
 356 +-------+------------+--------------------+----------------------------------------------+
 357 | 101   | !x9,off    | src=!x9, dest=none |                                              |
 358 +-------+------------+                    +----------------------------------------------+
 359 | 110   | off,!x10   | src=none, dest=!x10|                                              |
 360 +-------+------------+                    +----------------------------------------------+
 361 | 111   | !x9,!x10   | src=!x9, dest=!x10 |                                              |
 362 +-------+------------+--------------------+----------------------------------------------+
 363
 364 Integer Element Type (itype) Field Encoding
 365 ===========================================
 366
 367 +------------+-------+--------------+--------------+-----------------+-------------------+
 368 | Signedness | itype | Element Type | Mnemonic in  | Mnemonic in FP  | Meaning (INT may  |
 369 | [#sgn_def]_|       |              | Integer      | Instructions    | be un/signed, FP  |
 370 | [#sgn_def]_|       |              | Instructions | (such as fmv.x) | just re-sized     |
 371 +============+=======+==============+==============+=================+===================+
 372 | Unsigned   | 01    | u8           | BU           | BU              | Unsigned 8-bit    |
 373 |            +-------+--------------+--------------+-----------------+-------------------+
 374 |            | 10    | u16          | HU           | HU              | Unsigned 16-bit   |
 375 |            +-------+--------------+--------------+-----------------+-------------------+
 376 |            | 11    | u32          | WU           | WU              | Unsigned 32-bit   |
 377 |            +-------+--------------+--------------+-----------------+-------------------+
 378 |            | 00    | uXLEN        | WU/DU/QU     | WU/LU/TU        | Unsigned XLEN-bit |
 379 +------------+-------+--------------+--------------+-----------------+-------------------+
 380 | Signed     | 01    | i8           | BS           | BS              | Signed 8-bit      |
 381 |            +-------+--------------+--------------+-----------------+-------------------+
 382 |            | 10    | i16          | HS           | HS              | Signed 16-bit     |
 383 |            +-------+--------------+--------------+-----------------+-------------------+
 384 |            | 11    | i32          | W            | W               | Signed 32-bit     |
 385 |            +-------+--------------+--------------+-----------------+-------------------+
 386 |            | 00    | iXLEN        | W/D/Q        | W/L/T           | Signed XLEN-bit   |
 387 +------------+-------+--------------+--------------+-----------------+-------------------+
 388
 389 .. [#sgn_def] Signedness is defined in `Signedness Decision Procedure`_
 390
 391 Note: vector mode is effectively a type-cast of the register file
 392 as if it was a sequential array being typecast to typedef itype[]
 393 (c syntax).  The starting point of the "typecast" is the vector
 394 register rs#/rd.
 395
 396 Example: if itype=0b10 (u16), and rd is set to "vector", and
 397 VL is set to 4, the 64-bit register at rd is subdivided into
 398 *FOUR* 16-bit destination elements.  It is *NOT* four
 399 separate 64-bit destination registers (rd+0, rd+1, rd+2, rd+3)
 400 that are sign-extended from the source width size out to 64-bit,
 401 because that is itype=0b00 (uXLEN).
 402
 403 Note also: changing elwidth creates packed elements that, depending on VL, may create vectors that do not fit perfectly onto XLEM sized rehistry file boundaries. This does  NOT result in the destruction of the MSBs of the last register written to at the end of a VL loop. More details on how to handle this are described in the main Specification_.
 404
 405 Signedness Decision Procedure
 406 =============================
 407
 408 1. If the opcode field is either OP or OP-IMM, then
 409     1. Signedness is Unsigned.
 410 2. If the opcode field is either OP-32 or OP-IMM-32, then
 411     1. Signedness is Signed.
 412 3. If Signedness is encoded in a field of the base instruction, [#sign_enc]_ then
 413     1. Signedness uses the encoded value.
 414 4. Otherwise,
 415     1. Signedness is Unsigned.
 416
 417 .. [#sign_enc] Like in fcvt.d.l[u], but unlike in fmv.x.w, since there is no
 418                fmv.x.wu
 419
 420 Vector Type and Predication 5-bit (vtp5) Field Encoding
 421 =======================================================
 422
 423 In the following table, X denotes a wildcard that is 0 or 1 and can be a
 424 different value for every occurrence.
 425
 426 +-------+-----------+-----------+
 427 | vtp5  | pred      | svlen     |
 428 +=======+===========+===========+
 429 | 1XXXX | vtp5[4:2] | vtp5[1:0] |
 430 +-------+           |           |
 431 | 01XXX |           |           |
 432 +-------+           |           |
 433 | 000XX |           |           |
 434 +-------+-----------+-----------+
 435 | 001XX | *Reserved*            |
 436 +-------+-----------------------+
 437
 438 Vector Integer Type and Predication 6-bit (vitp6) Field Encoding
 439 ================================================================
 440
 441 In the following table, X denotes a wildcard that is 0 or 1 and can be a
 442 different value for every occurrence.
 443
 444 +--------+------------+---------+------------+------------+
 445 | vitp6  | itype      | pred[2] | pred[0:1]  | svlen      |
 446 +========+============+=========+============+============+
 447 | XX1XXX | vitp6[5:4] | 0       | vitp6[3:2] | vitp6[1:0] |
 448 +--------+            |         |            |            |
 449 | XX00XX |            |         |            |            |
 450 +--------+------------+---------+------------+------------+
 451 | XX01XX | *Reserved*                                     |
 452 +--------+------------------------------------------------+
 453
 454 vitp7 field: only tpred=
 455
 456 +---------+------------+----------+-------------+------------+
 457 | vitp7   | itype      | tpred[2] | tpred[0:1]  | svlen      |
 458 +=========+============+==========+=============+============+
 459 | XXXXXXX | vitp7[5:4] | vitp7[6] | vitp7[3:2]  | vitp7[1:0] |
 460 +---------+------------+----------+-------------+------------+
 461
 462 48-bit Instruction Encoding Decision Procedure
 463 ==============================================
 464
 465 In the following decision procedure, *Reserved* means that there is not yet a
 466 defined 48-bit instruction encoding for the base instruction.
 467
 468 1. If the base instruction is a load instruction, then
 469     a. If the base instruction is an I-type instruction, then
 470         1. The encoding is P48-LD-type.
 471     b. Otherwise
 472         1. The encoding is *Reserved*.
 473 2. If the base instruction is a store instruction, then
 474     a. If the base instruction is an S-type instruction, then
 475         1. The encoding is P48-ST-type.
 476     b. Otherwise
 477         1. The encoding is *Reserved*.
 478 3. If the base instruction is a SYSTEM instruction, then
 479     a. The encoding is *Reserved*.
 480 4. If the base instruction is an integer instruction, then
 481     a. If the base instruction is an R-type instruction, then
 482         1. The encoding is P48-R-type.
 483     b. If the base instruction is an I-type instruction, then
 484         1. The encoding is P48-I-type.
 485     c. If the base instruction is an S-type instruction, then
 486         1. The encoding is *Reserved*.
 487     d. If the base instruction is an B-type instruction, then
 488         1. The encoding is *Reserved*.
 489     e. If the base instruction is an U-type instruction, then
 490         1. The encoding is P48-U-type.
 491     f. If the base instruction is an J-type instruction, then
 492         1. The encoding is *Reserved*.
 493     g. Otherwise
 494         1. The encoding is *Reserved*.
 495 5. If the base instruction is a floating-point instruction, then
 496     a. If the base instruction is an R-type instruction, then
 497         1. The encoding is P48-FR-type.
 498     b. If the base instruction is an I-type instruction, then
 499         1. The encoding is P48-FI-type.
 500     c. If the base instruction is an S-type instruction, then
 501         1. The encoding is *Reserved*.
 502     d. If the base instruction is an B-type instruction, then
 503         1. The encoding is *Reserved*.
 504     e. If the base instruction is an U-type instruction, then
 505         1. The encoding is *Reserved*.
 506     f. If the base instruction is an J-type instruction, then
 507         1. The encoding is *Reserved*.
 508     g. If the base instruction is an R4-type instruction, then
 509         1. The encoding is P48-FR4-type.
 510     h. Otherwise
 511         1. The encoding is *Reserved*.
 512 6. Otherwise
 513     a. The encoding is *Reserved*.
 514
 515 CSR Registers
 516 =============
 517
 518 CSRs are the same as in the main Specification_, if associated functionality is implemented. They have the exact same meaning as in the main specification.
 519
 520 * VL
 521 * MVL
 522 * STATE
 523 * SUBVL
 524
 525 If svlen and VL/MVL overides are allowed in the 48 and 64 bit formats, the offsets during hardware loops need to be kept as internal state, and kept separate from the same in the main Specification_. Therefore an additional CSR set is needed (per priv level) named xSVSTATE
 526
 527 The format of the xSVSTATE CSR is identical to that in the main Specification_ as follows:
 528
 529 +---------+----------+----------+----------+----------+---------+---------+
 530 | (30..29 | (28..27) | (26..24) | (23..18) | (17..12) | (11..6) | (5...0) |
 531 +---------+----------+----------+----------+----------+---------+---------+
 532 | dsvoffs | ssvoffs  | subvl    | destoffs | srcoffs  | vl      | maxvl   |
 533 +---------+----------+----------+----------+----------+---------+---------+
 534
 535 SetVL
 536 =====
 537
 538 setvl rd, rs1, imm
 539 setvl rd, rs1
 540
 541 This is done the same as Standard SV.
 542 There is also a MVL CSR.  CSRRW and CSRRWI operate in the same way as in SV. See Specification_.
 543
 544
 545 Additional Instructions
 546 =======================
 547
 548 Add instructions to convert between integer types.
 549
 550 Add instructions to `swizzle`_ elements in sub-vectors. Note that the sub-vector
 551 lengths of the source and destination won't necessarily match.
 552
 553 .. _swizzle: https://www.khronos.org/opengl/wiki/Data_Type_(GLSL)#Swizzling
 554
 555 Add instructions to transpose (2-4)x(2-4) element matrices.
 556
 557 Add instructions to insert or extract a sub-vector from a vector, with the index
 558 allowed to be both immediate and from a register (*immediate can be covered partly
 559 by twin-predication, register cannot: requires MV.X aka VSELECT*)
 560
 561 Add a register gather instruction (aka MV.X)
 562
 563 # Open questions <a name="questions"></a>
 564
 565 Confirmation needed as to whether subvector extraction can be covered by twin predication (it probably can, it is one of the many purposes it is for).
 566
 567 --
 568
 569 What is SUBVL and how does it work
 570
 571 --
 572
 573 SVorig goes to a lot of effort to make VL 1<= MAXVL and MAXVL 1..64 where both CSRs may be stored internally in only 6 bits.
 574
 575 Thus, CSRRWI can reach 1..32 for VL and MAXVL.
 576
 577 In addition, setting a hardware loop to zero turning instructions into NOPs, um, just branch over them, to start the first loop at the end, on the test for loop variable being zero, a la c "while do" instead of "do while".
 578
 579 Or, does it not matter that VL only goes up to 31 on a CSRRWI, and that it only goes to a max of 63 rather than 64?
 580
 581 --
 582
 583 Should these questions be moved to Discussion subpage
 584
 585 --
 586
 587 Is MV.X good enough a substitute for swizzle?
 588
 589 --
 590
 591 Is vectorised srcbase ok as a gather scatter and ok substitute for register stride? 5 dependency registers (reg stride being the 5th) is quite scary
 592
 593 --
 594
 595 Why are integer conversion instructions needed, when the main SV spec covers them by allowing elwidth to be set on both src and dest regs?
 596
 597 --
 598
 599 Why are the SETVL rules so complex? What is the reason, how are loops carried out?
 600
 601 --
 602
 603 With SUBVL (sub vector len) being both a CSR and also part of the 48/64 bit opcode, how does that work?
 604
 605 --
 606
 607 What are the interaction rules when a 48/64 prefix opcode has a rd/rs that already has a Vector Context for either predication or a register?
 608
 609 It would perhaps make sense (and for svlen as well) to make 48/64 isolated and unaffected by VLIW context, with the exception of VL/MVL.
 610
 611 MVL and VL should be modifiable by 64 bit prefix as they are global in nature.
 612