simple_v_extension/sv_prefix_proposal.rst

   1 SimpleV Prefix (SVprefix) Proposal v0.3
   2 =======================================
   3
   4 * Copyright (c) Jacob Lifshay, 2019
   5 * Copyright (c) Luke Kenneth Casson Leighton, 2019
   6
   7 This proposal is designed to be able to operate without SVorig, but not to
   8 require the absence of SVorig. See Specification_.
   9
  10 Principle: SVprefix embeds (unmodified) RVC and 32-bit scalar opcodes
  11 into 32, 48 and 64 bit RV formats, to provide Vectorisation context
  12 on a per-instruction basis.
  13
  14 .. _Specification: http://libre-riscv.org/simple_v_extension/specification/
  15
  16 .. contents::
  17
  18 Conventions
  19 ===========
  20
  21 Conventions used in this document:
  22
  23 * Bits are numbered starting from 0 at the LSB, so bit 3 is 1 in the integer 8.
  24 * Bit ranges are inclusive on both ends, so 5:3 means bits 5, 4, and 3.
  25 * Operations work on variable-length vectors of sub-vectors up to *VL*
  26   in length, where each sub-vector has a length *svlen*, and *svlen*
  27   elements of type *etype*.
  28 * The actual total number of elements is therefore *svlen* times *VL*.
  29 * When the vectors are stored in registers, all elements are packed so
  30   that there is no padding in-between elements of the same vector.
  31 * The register file itself is thus best viewed as a byte-level SRAM that
  32   is typecast to an array of *etypes*
  33 * The number of bytes in a sub-vector, *svsz*, is the product of *svlen*
  34   and the element size in bytes.
  35
  36 Options
  37 =======
  38
  39 The following partial / full implementation options are possible:
  40
  41 * SVPrefix augments the main Specification_
  42 * SVPrefix operates independently, without the main spec VL (and MVL)
  43   CSRs (in any priv level)
  44 * SVPrefix operates independently, without the main spec SUBVL CSRs
  45   (in any priv level)
  46 * SVPrefix has no support for VL (or MVL) overrides in the 64 bit
  47   instruction format (VLtyp=0 as the only legal permitted value)
  48 * SVPrefix has no support for svlen overrides in either the 48 or 64
  49   bit instruction format either (svlen=0 as the only legal permitted value).
  50
  51 All permutations of the above options are permitted, and the UNIX
  52 platform must raise illegal instruction exceptions on implementations
  53 that do not support each option.  For example, an implementation that
  54 has no support for VLtyp that sees an opcode with a nonzero VLtyp must
  55 raise an illegal instruction exception.
  56
  57 Note that SVPrefix (VLtyp and svlen) has its own STATE CSR, SVPSTATE. This allows Prefixed operations to be re-entrant on traps, and to not affect VBLOCK use of VL or SUBVL.
  58
  59 If the main Specification_ CSRs and features are to be supported (VBLOCK), then when VLtyp or svlen are "default" they utilise the main Specification_ VBLOCK VL and/or SUBVL, and, correspondingly, the main VBLOCK STATE CSR will be updated and used to track hardware loops.
  60
  61 If however VLtyp is set to nondefault, then the SVPSTATE src and destoffs fields are used instead to create the hardware loops, and likewise if svlen is set to nondefault, SVPSTATE's svoffs field is used.
  62
  63 Half-Precision Floating Point (FP16)
  64 ====================================
  65
  66 If the F extension is supported, SVprefix adds support for FP16 in the
  67 base FP instructions by using 10 (H) in the floating-point format field
  68 *fmt* and using 001 (H) in the floating-point load/store *width* field.
  69
  70 Compressed Instructions
  71 =======================
  72
  73 Compressed instructions are under evaluation by taking the same
  74 prefix as used in P48, embedding that and standard RVC opcodes (minus
  75 their RVC prefix) into a 32-bit space.  This by taking the three remaining
  76 Major "custom" opcodes (0-2), one for each of the three RVC Quadrants.
  77 see [[discussion]].
  78
  79 48-bit Prefixed Instructions
  80 ============================
  81
  82 All 48-bit prefixed instructions contain a 32-bit "base" instruction as
  83 the last 4 bytes. Since all 32-bit instructions have bits 1:0 set to
  84 11, those bits are reused for additional encoding space in the 48-bit
  85 instructions.
  86
  87 64-bit Prefixed Instructions
  88 ============================
  89
  90 The 48 bit format is further extended with the full 128-bit range on all
  91 source and destination registers, and the option to set both SVSTATE.VL and SVSTATE.MVL
  92 is provided.
  93
  94 48-bit Instruction Encodings
  95 ============================
  96
  97 In the following table, *Rsvd* (reserved) entries must be zero.  RV32 equivalent
  98 encodings included for side-by-side comparison (and listed below,
  99 separately).
 100
 101 First, bits 17:0:
 102
 103 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 104 | Encoding      | 17     | 16     | 15       | 14  | 13     | 12          | 11:7 | 6      | 5:0    |
 105 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 106 | P48-LD-type   | rd[5]  | rs1[5] | vitp7[6] | vd  | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
 107 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 108 | P48-ST-type   |vitp7[6]| rs1[5] | rs2[5]   | vs2 | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
 109 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 110 | P48-R-type    | rd[5]  | rs1[5] | rs2[5]   | vs2 | vs1    | vitp6              | *Rsvd* | 011111 |
 111 +---------------+--------+--------+----------+-----+--------+--------------------+--------+--------+
 112 | P48-I-type    | rd[5]  | rs1[5] | vitp7[6] | vd  | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
 113 +---------------+--------+--------+----------+-----+--------+--------------------+--------+--------+
 114 | P48-U-type    | rd[5]  | *Rsvd* | *Rsvd*   | vd  | *Rsvd* | vitp6              | *Rsvd* | 011111 |
 115 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 116 | P48-FR-type   | rd[5]  | rs1[5] | rs2[5]   | vs2 | vs1    | *Rsvd*      | vtp5 | *Rsvd* | 011111 |
 117 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 118 | P48-FI-type   | rd[5]  | rs1[5] | vitp7[6] | vd  | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
 119 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 120 | P48-FR4-type  | rd[5]  | rs1[5] | rs2[5]   | vs2 | rs3[5] | vs3 [#fr4]_ | vtp5 | *Rsvd* | 011111 |
 121 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 122
 123 .. [#fr4] Only vs2 and vs3 are included in the P48-FR4-type encoding
 124           because there is not enough space for vs1 as well, and because
 125           it is more useful to have a scalar argument for each of the
 126           multiplication and addition portions of fmadd than to have
 127           two scalars on the multiplication portion.
 128
 129 Table showing correspondance between P48-*-type and RV32-*-type.
 130 These are bits 47:18 (RV32 shifted up by 16 bits):
 131
 132 +---------------+---------------+
 133 | Encoding      | RV32 Encoding |
 134 +---------------+---------------+
 135 | 47:32         | 31:2          |
 136 +---------------+---------------+
 137 | P48-LD-type   | RV32-I-type   |
 138 +---------------+---------------+
 139 | P48-ST-type   | RV32-S-Type   |
 140 +---------------+---------------+
 141 | P48-R-type    | RV32-R-Type   |
 142 +---------------+---------------+
 143 | P48-I-type    | RV32-I-Type   |
 144 +---------------+---------------+
 145 | P48-U-type    | RV32-U-Type   |
 146 +---------------+---------------+
 147 | P48-FR-type   | RV32-FR-Type  |
 148 +---------------+---------------+
 149 | P48-FI-type   | RV32-I-Type   |
 150 +---------------+---------------+
 151 | P48-FR4-type  | RV32-FR4-type |
 152 +---------------+---------------+
 153
 154 Table showing Standard RV32 encodings:
 155
 156 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 157 | Encoding      | 31:27       | 26:25 | 24:20    | 19:15    | 14:12  | 11:7     | 6:2    | 1:0    |
 158 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 159 | RV32-R-type   +    funct7           + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0]  + opcode + 0b11   |
 160 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 161 | RV32-S-type   + imm[11:5]           + rs2[4:0] + rs1[4:0] + funct3 | imm[4:0] + opcode + 0b11   |
 162 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 163 | RV32-I-type   + imm[11:0]                      + rs1[4:0] + funct3 | rd[4:0]  + opcode + 0b11   |
 164 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 165 | RV32-U-type   + imm[31:12]                                         | rd[4:0]  + opcode + 0b11   |
 166 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 167 | RV32-FR4-type + rs3[4:0]    + fmt   + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0]  + opcode + 0b11   |
 168 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 169 | RV32-FR-type  + funct5      + fmt   + rs2[4:0] + rs1[4:0] + rm     | rd[4:0]  + opcode + 0b11   |
 170 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 171
 172 64-bit Instruction Encodings
 173 ============================
 174
 175 Where in the 48 bit format the prefix is "0b0011111" in bits 0 to 6,
 176 this is now set to "0b0111111".
 177
 178 +---------------+---------------+--------------+-----------+
 179 | 63:48         | 47:18         | 17:7         | 6:0       |
 180 +---------------+---------------+--------------+-----------+
 181 | 64 bit prefix | RV32[31:3]    | P48[17:7]    | 0b0111111 |
 182 +---------------+---------------+--------------+-----------+
 183
 184 * The 64 bit prefix format is below
 185 * Bits 18 to 47 contain bits 3 to 31 of a standard RV32 format
 186 * Bits 7 to 17 contain bits 7 through 17 of the P48 format
 187 * Bits 0 to 6 contain the standard RV 64-bit prefix 0b0111111
 188
 189 64 bit prefix format:
 190
 191 +--------------+-------+--------+--------+--------+--------+
 192 | Encoding     | 63    | 62     | 61     | 60     | 59:48  |
 193 +--------------+-------+--------+--------+--------+--------+
 194 | P64-LD-type  | rd[6] | rs1[6] |        | *Rsvd* | VLtyp  |
 195 +--------------+-------+--------+--------+--------+--------+
 196 | P64-ST-type  |       | rs1[6] | rs2[6] | *Rsvd* | VLtyp  |
 197 +--------------+-------+--------+--------+--------+--------+
 198 | P64-R-type   | rd[6] | rs1[6] | rs2[6] | vd     | VLtyp  |
 199 +--------------+-------+--------+--------+--------+--------+
 200 | P64-I-type   | rd[6] | rs1[6] |        | *Rsvd* | VLtyp  |
 201 +--------------+-------+--------+--------+--------+--------+
 202 | P64-U-type   | rd[6] |        |        | *Rsvd* | VLtyp  |
 203 +--------------+-------+--------+--------+--------+--------+
 204 | P64-FR-type  |       | rs1[6] | rs2[6] | vd     | VLtyp  |
 205 +--------------+-------+--------+--------+--------+--------+
 206 | P64-FI-type  | rd[6] | rs1[6] | rs2[6] | vd     | VLtyp  |
 207 +--------------+-------+--------+--------+--------+--------+
 208 | P64-FR4-type | rd[6] | rs1[6] | rs2[6] | rs3[6] | VLtyp  |
 209 +--------------+-------+--------+--------+--------+--------+
 210
 211 The extra bit for src and dest registers provides the full range of
 212 up to 128 registers, when combined with the extra bit from the 48 bit
 213 prefix as well.  VLtyp encodes how (whether) to set SVPSTATE.VL and SVPSTATE.MAXVL.
 214
 215 VLtyp field encoding
 216 ====================
 217
 218 NOTE: VL and MVL below are local to SVPrefix and, if non-default,
 219 will update the src and dest element offsets in SVPSTATE, not the main
 220 Specification_ STATE. If default (all zeros) then STATE VL and MVL apply
 221 to this instruction, and STATE.srcoffs (etc) will be used.
 222
 223 +-----------+-------------+--------------+----------+----------------------+
 224 | VLtyp[11] | VLtyp[10:6] | VLtyp[5:1]   | VLtyp[0] | comment              |
 225 +-----------+-------------+--------------+----------+----------------------+
 226 | 0         |  00000      | 00000        |  0       | no change to VL/MVL  |
 227 +-----------+-------------+--------------+----------+----------------------+
 228 | 0         |  VLdest     | VLEN         |  vlt     | VL imm/reg mode (vlt)|
 229 +-----------+-------------+--------------+----------+----------------------+
 230 | 1         |  VLdest     | MVL+VL-immed | 0        | MVL+VL immed mode    |
 231 +-----------+-------------+--------------+----------+----------------------+
 232 | 1         |  VLdest     |  MVL-immed   | 1        | MVL immed mode       |
 233 +-----------+-------------+--------------+----------+----------------------+
 234
 235 Note: when VLtyp is all zeros, the main Specification_ VL and MVL apply
 236 to this instruction. If called outside of a VBLOCK or if sv.setvl has
 237 not set VL, the operation is "scalar".
 238
 239 Just as in the VBLOCK format, when bit 11 of VLtyp is zero:
 240
 241 * if vlt is zero, bits 1 to 5 specify the VLEN as a 5 bit immediate
 242   (offset by 1: 0b00000 represents VL=1, 0b00001 represents VL=2 etc.)
 243 * if vlt is 1, bits 1 to 5 specify the scalar (RV standard) register
 244   from which VL is set.  x0 is not permitted
 245 * VL goes into the scalar register VLdest (if VLdest is not x0)
 246
 247 When bit 11 of VLtype is 1:
 248
 249 * if VLtyp[0] is zero, both SVPSTATE.MAXVL and SVPSTATE.VL are set to (imm+1).  The same
 250   value goes into the scalar register VLdest (if VLdest is not x0)
 251 * if VLtyp[0] is 1, SVPSTATE.MAXVL is set to (imm+1).
 252   SVPSTATE.VL will be truncated to within the new range (if VL was greater
 253   than the new MAXVL).  The new VL goes into the scalar register VLdest
 254   (if VLdest is not x0).
 255
 256 This gives the option to set up SVPSTATE.VL in a "loop mode" (VLtype[11]=0) or
 257 in a "one-off" mode (VLtype[11]=1) which sets both MVL and VL to the
 258 same immediate value.  This may be most useful for one-off Vectorised
 259 operations such as LOAD-MULTI / STORE-MULTI, for saving and restoration
 260 of large batches of registers in context-switches or function calls.
 261
 262 Note that VLtyp's VL and MVL are not the same as the main Specification_
 263 VL or MVL, and that loops will alter srcoffs and destoffs in SVPSTATE in VLtype nondefault mode, but the srcoffs and destoffs in STATE, if VLtype=0.
 264
 265 Furthermore, the execution order and exception handling must be exactly
 266 the same as in the main spec (Program Order must be preserved)
 267
 268 Pseudocode for SVPSTATE.VL:
 269
 270 .. parsed-literal::
 271
 272     # pseudocode
 273
 274     regs = [0u64; 128];
 275     vl = 0;
 276
 277     // instruction fields:
 278     rd = get_rd_field();
 279     vlmax = get_immed_field();
 280
 281     // handle illegal instruction decoding
 282     if vlmax > XLEN {
 283         trap()
 284     }
 285
 286     // calculate VL
 287     if rs1 == 0 { // rs1 is x0
 288         vl = vlmax
 289     } else {
 290         vl = min(regs[rs1], vlmax)
 291     }
 292
 293     // write rd
 294     if rd != 0 {
 295         // rd is not x0
 296         regs[rd] = vl
 297     }
 298
 299 vs#/vd Fields' Encoding
 300 =======================
 301
 302 +--------+----------+----------------------------------------------------------+
 303 | vs#/vd | Mnemonic | Meaning                                                  |
 304 +========+==========+==========================================================+
 305 | 0      | S        | the rs#/rd field specifies a scalar (single sub-vector); |
 306 |        |          | the rs#/rd field is zero-extended to get the actual      |
 307 |        |          | 7-bit register number                                    |
 308 +--------+----------+----------------------------------------------------------+
 309 | 1      | V        | the rs#/rd field specifies a vector; the rs#/rd field is |
 310 |        |          | decoded using the `Vector Register Number Encoding`_ to  |
 311 |        |          | get the actual 7-bit register number                     |
 312 +--------+----------+----------------------------------------------------------+
 313
 314 If a vs#/vd field is not present, it is as if it was present with a value that
 315 is the bitwise-or of all present vs#/vd fields.
 316
 317 * scalar register numbers do NOT increment when allocated in the
 318   hardware for-loop.  the same scalar register number is handed
 319   to every ALU.
 320
 321 * vector register numbers *DO* increase when allocated in the
 322   hardware for-loop.  sequentially-increasing register data
 323   is handed to sequential ALUs.
 324
 325 Vector Register Number Encoding
 326 ===============================
 327
 328 For the 48 bit format, when vs#/vd is 1, the actual 7-bit register number
 329 is derived from the corresponding 6-bit rs#/rd field:
 330
 331 +---------------------------------+
 332 | Actual 7-bit register number    |
 333 +===========+=============+=======+
 334 | Bit 6     | Bits 5:1    | Bit 0 |
 335 +-----------+-------------+-------+
 336 | rs#/rd[0] | rs#/rd[5:1] | 0     |
 337 +-----------+-------------+-------+
 338
 339 For the 64 bit format, the 7 bit register is constructed from the 7 bit
 340 fields: bits 0 to 4 from the 32 bit RV Standard format, bit 5 from the 48
 341 bit prefix and bit 6 from the 64 bit prefix.  Thus in the 64 bit format
 342 the full range of up to 128 registers is directly available. This for
 343 both when either scalar or vector mode is set.
 344
 345 Load/Store Kind (lsk) Field Encoding
 346 ====================================
 347
 348 +--------+-----+--------------------------------------------------------------------------------+
 349 | vd/vs2 | vs1 | Meaning                                                                        |
 350 +========+=====+================================================================================+
 351 | 0      | 0   | srcbase is scalar, LD/ST is pure scalar.                                       |
 352 +--------+-----+--------------------------------------------------------------------------------+
 353 | 1      | 0   | srcbase is scalar, LD/ST is unit strided                                       |
 354 +--------+-----+--------------------------------------------------------------------------------+
 355 | 0      | 1   | srcbase is a vector (gather/scatter aka array of srcbases). VSPLAT and VSELECT |
 356 +--------+-----+--------------------------------------------------------------------------------+
 357 | 1      | 1   | srcbase is a vector, LD/ST is a full vector LD/ST.                             |
 358 +--------+-----+--------------------------------------------------------------------------------+
 359
 360 Notes:
 361
 362 * A register strided LD/ST would require *5* registers. srcbase, vd/vs2,
 363   predicate 1, predicate 2 and the stride register.
 364 * Complex strides may all be done with a general purpose vector of srcbases.
 365 * Twin predication may be used even when vd/vs1 is a scalar, to give
 366   VSPLAT and VSELECT, because the hardware loop ends on the first occurrence
 367   of a 1 in the predicate when a predicate is applied to a scalar.
 368 * Full vectorised gather/scatter is enabled when both registers are
 369   marked as vectorised, however unlike e.g Intel AVX512, twin predication
 370   can be applied.
 371
 372 Open question: RVV overloads the width field of LOAD-FP/STORE-FP
 373 using the bit 2 to indicate additional interpretation of the 11 bit
 374 immediate. Should this be considered?
 375
 376
 377 Sub-Vector Length (svlen) Field Encoding
 378 ========================================
 379
 380 NOTE: svlen is not the same as the main spec SUBVL.  When nondefault (not zero) SVPSTATE context is used for Sub vector loops. However is svlen is zero, STATE and SUBVL is used instead.
 381
 382 Bitwidth, from VL's perspective, is a multiple of the elwidth times svlen.
 383 So within each loop of VL there are svlen sub-elements of elwidth in size,
 384 just like in a SIMD architecture. When svlen is set to 0b00 (indicating
 385 svlen=1) no such SIMD-like behaviour exists and the subvectoring is
 386 disabled.
 387
 388 Predicate bits do not apply to the individual sub-vector elements, they
 389 apply to the entire subvector group. This saves instructions on setup
 390 of the predicate.
 391
 392 +----------------+-------+
 393 | svlen Encoding | Value |
 394 +================+=======+
 395 | 00             | SUBVL |
 396 +----------------+-------+
 397 | 01             | 2     |
 398 +----------------+-------+
 399 | 10             | 3     |
 400 +----------------+-------+
 401 | 11             | 4     |
 402 +----------------+-------+
 403
 404 In independent standalone implementations that do not implement the
 405 main specification, the value of SUBVL in the above table (svtyp=0b00)
 406 is set to 1, such that svlen is also 1.
 407
 408 Behaviour of operations that set svlen are identical to those of the
 409 main spec. See section on VLtyp, above.
 410
 411 Predication (pred) Field Encoding
 412 =================================
 413
 414 +------+------------+--------------------+----------------------------------------+
 415 | pred | Mnemonic   | Predicate Register | Meaning                                |
 416 +======+============+====================+========================================+
 417 | 000  | *None*     | *None*             | The instruction is unpredicated        |
 418 +------+------------+--------------------+----------------------------------------+
 419 | 001  | *Reserved* | *Reserved*         |                                        |
 420 +------+------------+--------------------+----------------------------------------+
 421 | 010  | !x9        | x9 (s1)            | execute vector op[0..i] on x9[i] == 0  |
 422 +------+------------+                    +----------------------------------------+
 423 | 011  | x9         |                    | execute vector op[0..i] on x9[i] == 1  |
 424 +------+------------+--------------------+----------------------------------------+
 425 | 100  | !x10       | x10 (a0)           | execute vector op[0..i] on x10[i] == 0 |
 426 +------+------------+                    +----------------------------------------+
 427 | 101  | x10        |                    | execute vector op[0..i] on x10[i] == 1 |
 428 +------+------------+--------------------+----------------------------------------+
 429 | 110  | !x11       | x11 (a1)           | execute vector op[0..i] on x11[i] == 0 |
 430 +------+------------+                    +----------------------------------------+
 431 | 111  | x11        |                    | execute vector op[0..i] on x11[i] == 1 |
 432 +------+------------+--------------------+----------------------------------------+
 433
 434 Twin-predication (tpred) Field Encoding
 435 =======================================
 436
 437 +-------+------------+--------------------+----------------------------------------------+
 438 | tpred | Mnemonic   | Predicate Register | Meaning                                      |
 439 +=======+============+====================+==============================================+
 440 | 000   | *None*     | *None*             | The instruction is unpredicated              |
 441 +-------+------------+--------------------+----------------------------------------------+
 442 | 001   | x9,off     | src=x9, dest=none  | src[0..i] uses x9[i], dest unpredicated      |
 443 +-------+------------+                    +----------------------------------------------+
 444 | 010   | off,x10    | src=none, dest=x10 | dest[0..i] uses x10[i], src unpredicated     |
 445 +-------+------------+                    +----------------------------------------------+
 446 | 011   | x9,10      | src=x9, dest=x10   | src[0..i] uses x9[i], dest[0..i] uses x10[i] |
 447 +-------+------------+--------------------+----------------------------------------------+
 448 | 100   | *None*     | *RESERVED*         | Instruction is unpredicated (TBD)            |
 449 +-------+------------+--------------------+----------------------------------------------+
 450 | 101   | !x9,off    | src=!x9, dest=none |                                              |
 451 +-------+------------+                    +----------------------------------------------+
 452 | 110   | off,!x10   | src=none, dest=!x10|                                              |
 453 +-------+------------+                    +----------------------------------------------+
 454 | 111   | !x9,!x10   | src=!x9, dest=!x10 |                                              |
 455 +-------+------------+--------------------+----------------------------------------------+
 456
 457 Integer Element Type (itype) Field Encoding
 458 ===========================================
 459
 460 +------------+-------+--------------+--------------+-----------------+-------------------+
 461 | Signedness | itype | Element Type | Mnemonic in  | Mnemonic in FP  | Meaning (INT may  |
 462 | [#sgn_def]_|       |              | Integer      | Instructions    | be un/signed, FP  |
 463 | [#sgn_def]_|       |              | Instructions | (such as fmv.x) | just re-sized     |
 464 +============+=======+==============+==============+=================+===================+
 465 | Unsigned   | 01    | u8           | BU           | BU              | Unsigned 8-bit    |
 466 |            +-------+--------------+--------------+-----------------+-------------------+
 467 |            | 10    | u16          | HU           | HU              | Unsigned 16-bit   |
 468 |            +-------+--------------+--------------+-----------------+-------------------+
 469 |            | 11    | u32          | WU           | WU              | Unsigned 32-bit   |
 470 |            +-------+--------------+--------------+-----------------+-------------------+
 471 |            | 00    | uXLEN        | WU/DU/QU     | WU/LU/TU        | Unsigned XLEN-bit |
 472 +------------+-------+--------------+--------------+-----------------+-------------------+
 473 | Signed     | 01    | i8           | BS           | BS              | Signed 8-bit      |
 474 |            +-------+--------------+--------------+-----------------+-------------------+
 475 |            | 10    | i16          | HS           | HS              | Signed 16-bit     |
 476 |            +-------+--------------+--------------+-----------------+-------------------+
 477 |            | 11    | i32          | W            | W               | Signed 32-bit     |
 478 |            +-------+--------------+--------------+-----------------+-------------------+
 479 |            | 00    | iXLEN        | W/D/Q        | W/L/T           | Signed XLEN-bit   |
 480 +------------+-------+--------------+--------------+-----------------+-------------------+
 481
 482 .. [#sgn_def] Signedness is defined in `Signedness Decision Procedure`_
 483
 484 Note: vector mode is effectively a type-cast of the register file
 485 as if it was a sequential array being typecast to typedef itype[]
 486 (c syntax).  The starting point of the "typecast" is the vector
 487 register rs#/rd.
 488
 489 Example: if itype=0b10 (u16), and rd is set to "vector", and
 490 VL is set to 4, the 64-bit register at rd is subdivided into
 491 *FOUR* 16-bit destination elements.  It is *NOT* four
 492 separate 64-bit destination registers (rd+0, rd+1, rd+2, rd+3)
 493 that are sign-extended from the source width size out to 64-bit,
 494 because that is itype=0b00 (uXLEN).
 495
 496 Note also: changing elwidth creates packed elements that, depending on
 497 VL, may create vectors that do not fit perfectly onto XLEN sized registry
 498 file bit-boundaries. This does NOT result in the destruction of the MSBs
 499 of the last register written to at the end of a VL loop. More details
 500 on how to handle this are described in the main Specification_.
 501
 502 Signedness Decision Procedure
 503 =============================
 504
 505 1. If the opcode field is either OP or OP-IMM, then
 506     1. Signedness is Unsigned.
 507 2. If the opcode field is either OP-32 or OP-IMM-32, then
 508     1. Signedness is Signed.
 509 3. If Signedness is encoded in a field of the base instruction, [#sign_enc]_ then
 510     1. Signedness uses the encoded value.
 511 4. Otherwise,
 512     1. Signedness is Unsigned.
 513
 514 .. [#sign_enc] Like in fcvt.d.l[u], but unlike in fmv.x.w,
 515                since there is no fmv.x.wu
 516
 517 Vector Type and Predication 5-bit (vtp5) Field Encoding
 518 =========================================================
 519
 520 In the following table, X denotes a wildcard that is 0 or 1 and can be
 521 a different value for every occurrence.
 522
 523 +-------+-----------+-----------+
 524 | vtp5  | pred      | svlen     |
 525 +=======+===========+===========+
 526 | 1XXXX | vtp5[4:2] | vtp5[1:0] |
 527 +-------+           |           |
 528 | 01XXX |           |           |
 529 +-------+           |           |
 530 | 000XX |           |           |
 531 +-------+-----------+-----------+
 532 | 001XX | *Reserved*            |
 533 +-------+-----------------------+
 534
 535 Vector Integer Type and Predication 6-bit (vitp6) Field Encoding
 536 =================================================================
 537
 538 In the following table, X denotes a wildcard that is 0 or 1 and can be a
 539 different value for every occurrence.
 540
 541 +--------+------------+---------+------------+------------+
 542 | vitp6  | itype      | pred[2] | pred[0:1]  | svlen      |
 543 +========+============+=========+============+============+
 544 | XX1XXX | vitp6[5:4] | 0       | vitp6[3:2] | vitp6[1:0] |
 545 +--------+            |         |            |            |
 546 | XX00XX |            |         |            |            |
 547 +--------+------------+---------+------------+------------+
 548 | XX01XX | *Reserved*                                     |
 549 +--------+------------------------------------------------+
 550
 551 vitp7 field: only tpred
 552
 553 +---------+------------+----------+-------------+------------+
 554 | vitp7   | itype      | tpred[2] | tpred[0:1]  | svlen      |
 555 +=========+============+==========+=============+============+
 556 | XXXXXXX | vitp7[5:4] | vitp7[6] | vitp7[3:2]  | vitp7[1:0] |
 557 +---------+------------+----------+-------------+------------+
 558
 559 48-bit Instruction Encoding Decision Procedure
 560 ==============================================
 561
 562 In the following decision procedure, *Reserved* means that there is not
 563 yet a defined 48-bit instruction encoding for the base instruction.
 564
 565 1. If the base instruction is a load instruction, then
 566     a. If the base instruction is an I-type instruction, then
 567         1. The encoding is P48-LD-type.
 568     b. Otherwise
 569         1. The encoding is *Reserved*.
 570 2. If the base instruction is a store instruction, then
 571     a. If the base instruction is an S-type instruction, then
 572         1. The encoding is P48-ST-type.
 573     b. Otherwise
 574         1. The encoding is *Reserved*.
 575 3. If the base instruction is a SYSTEM instruction, then
 576     a. The encoding is *Reserved*.
 577 4. If the base instruction is an integer instruction, then
 578     a. If the base instruction is an R-type instruction, then
 579         1. The encoding is P48-R-type.
 580     b. If the base instruction is an I-type instruction, then
 581         1. The encoding is P48-I-type.
 582     c. If the base instruction is an S-type instruction, then
 583         1. The encoding is *Reserved*.
 584     d. If the base instruction is an B-type instruction, then
 585         1. The encoding is *Reserved*.
 586     e. If the base instruction is an U-type instruction, then
 587         1. The encoding is P48-U-type.
 588     f. If the base instruction is an J-type instruction, then
 589         1. The encoding is *Reserved*.
 590     g. Otherwise
 591         1. The encoding is *Reserved*.
 592 5. If the base instruction is a floating-point instruction, then
 593     a. If the base instruction is an R-type instruction, then
 594         1. The encoding is P48-FR-type.
 595     b. If the base instruction is an I-type instruction, then
 596         1. The encoding is P48-FI-type.
 597     c. If the base instruction is an S-type instruction, then
 598         1. The encoding is *Reserved*.
 599     d. If the base instruction is an B-type instruction, then
 600         1. The encoding is *Reserved*.
 601     e. If the base instruction is an U-type instruction, then
 602         1. The encoding is *Reserved*.
 603     f. If the base instruction is an J-type instruction, then
 604         1. The encoding is *Reserved*.
 605     g. If the base instruction is an R4-type instruction, then
 606         1. The encoding is P48-FR4-type.
 607     h. Otherwise
 608         1. The encoding is *Reserved*.
 609 6. Otherwise
 610     a. The encoding is *Reserved*.
 611
 612 CSR Registers
 613 =============
 614
 615 CSRs are the same as in the main Specification_, if associated
 616 functionality is implemented. They have the exact same meaning as in
 617 the main specification.
 618
 619 * VL
 620 * MVL
 621 * SVPSTATE
 622 * SUBVL
 623
 624 Associated SET and GET on the CSRs is exactly as in the main spec as well
 625 (including CSRRWI and CSRRW differences).
 626
 627 Note that if both VLtyp and svlen are not implemented, SVPSTATE is not required. Also if VL and SUBVL are not implemented, STATE from the main Specification_ is not required either.
 628
 629 However if partial functionality is implemented, the unimplemented bits
 630 in STATE and SVPSTATE must be zero, and, in the UNIX Platform, an illegal exception
 631 **MUST** be raised if unsupported bits are written to.
 632
 633 SVPSTATE fields are exactly the same layout as STATE:
 634
 635 +----------+----------+----------+----------+----------+---------+---------+
 636 | (31..28) | (27..26) | (25..24) | (23..18) | (17..12) | (11..6) | (5...0) |
 637 +----------+----------+----------+----------+----------+---------+---------+
 638 | rsvd     | dsvoffs  | subvl    | destoffs | srcoffs  | vl      | maxvl   |
 639 +----------+----------+----------+----------+----------+---------+---------+
 640
 641 However note that where STATE stores the scalar register number to be used as VL, SVPSTATE.VL actually contains the actual VL value, in an identical fashion to RVV.
 642
 643 Additional Instructions
 644 =======================
 645
 646 * Add instructions to convert between integer types.
 647 * Add instructions to `swizzle`_ elements in sub-vectors. Note that
 648   the sub-vector lengths of the source and destination won't necessarily
 649   match.
 650 * Add instructions to transpose (2-4)x(2-4) element matrices.
 651 * Add instructions to insert or extract a sub-vector from a vector, with
 652   the index allowed to be both immediate and from a register (*immediate
 653   can be covered by twin-predication, register might be, by virtue of
 654   predicates being registers*)
 655 * Add a register gather instruction (aka MV.X: regfile[rd] =
 656   regfile[regfile[rs1]])
 657
 658 subelement swizzle example:
 659
 660     velswizzle x32, x64, SRCSUBVL=3, DESTSUBVL=4, ELTYPE=u8, elements=[0, 0, 2, 1]
 661
 662 .. _swizzle: https://www.khronos.org/opengl/wiki/Data_Type_(GLSL)#Swizzling
 663
 664 questions
 665 =========
 666
 667 Moved to the discussion page (link at top of this page)
 668
 669 TODO
 670 ====
 671
 672 Work out a way to do sub-element swizzling.
 673