1 SimpleV Prefix (SVprefix) Proposal v0.3
2 =======================================
4 This proposal is designed to be able to operate without SVorig, but not to
5 require the absence of SVorig See Specification_.
7 .. _Specification: http://libre-riscv.org/simple_v_extension/specification/
14 Conventions used in this document:
15 - Bits are numbered starting from 0 at the LSB, so bit 3 is 1 in the integer 8.
16 - Bit ranges are inclusive on both ends, so 5:3 means bits 5, 4, and 3.
18 Operations work on variable-length vectors of sub-vectors, where each sub-vector
19 has a length *svlen*, and an element type *etype*. When the vectors are stored
20 in registers, all elements are packed so that there is no padding in-between
21 elements of the same vector. The number of bytes in a sub-vector, *svsz*, is the
22 product of *svlen* and the element size in bytes.
27 * SVPrefix augments the main Specification_
28 * SVPregix operates independently, without the main spec VL (and MVL) CSRs (in any priv level)
29 * SVPrefix operates independently, without the main spec SUBVL CSRs (in any priv level)
30 * SVPrefix operates independently, with no support for VL (or MVL) overrides in the 64 bit instruction format either (VLtyp=0 as the only legal permitted value)
31 * SVPrefix operates independently, with no support for svlen overrides in either the 48 or 64 bit instruction format either (svlen=0 as the only legal permitted value).
33 All permutations of the above options are permitted, and in the UNIX platform must raise illegal instruction exceptions on implementations that do not support them.
35 Note that SVPrefix (VLtyp and svlen) and the main spec share (modify) the STATE CSR. P48 and P64 opcodes must **NOT** set VLtyp or svlen inside loops that also use VL or SUBVL. Doing so will result in undefined behaviour, as STATE will be affected by doing so.
37 However, using VLtyp or svlen in standalone operations, or pushing (and restoring) the contents of the STATE CSR to the stack, or just storing its contents in a temporary register whilst executing a sequence of P48 or P64 opcodes, is perfectly fine.
39 If the main Specification_ CSRs are to be supported, the STATE, VL, MVL and SUBVL CSRs all operate according to the main specification. Under the options above, hypothetically an implementor could choose not to support setting of VL, MVL or SUBVL (only allowing them to be set to a value of 1). Under such circumstances, where *neither* VL/MVL *nor* SUBVL are supported, STATE would then not be required either.
41 If however support for SUBVL is to be provided, storing of the sub-vector offsets and SUBVL itself (and context switching of the same) in the STATE CSRs are mandatory.
43 Likewise if support for VL is to be provided, storing of VL, MVL and the dest and src offsets (and context switching of the same) in the STATE CSRs are mandatory.
46 Half-Precision Floating Point (FP16)
47 ====================================
49 If the F extension is supported, SVprefix adds support for FP16 in the
50 base FP instructions by using 10 (H) in the floating-point format field *fmt*
51 and using 001 (H) in the floating-point load/store *width* field.
53 Compressed Instructions
54 =======================
55 This proposal does not include any prefixed RVC instructions, instead, it will
56 include 32-bit instructions that are compressed forms of SVprefix 48-bit
57 instructions, in the same manner that RVC instructions are compressed forms of
58 RVI instructions. The compressed instructions will be defined later by
59 considering which 48-bit instructions are the most common.
61 48-bit Prefixed Instructions
62 ============================
63 All 48-bit prefixed instructions contain a 32-bit "base" instruction as the
64 last 4 bytes. Since all 32-bit instructions have bits 1:0 set to 11, those bits
65 are reused for additional encoding space in the 48-bit instructions.
67 64-bit Prefixed Instructions
68 ============================
70 The 48 bit format is further extended with the full 128-bit range on all source
71 and destination registers, and the option to set both VL and MVL is provided.
73 48-bit Instruction Encodings
74 ============================
76 In the following table, *Reserved* entries must be zero. RV32 equivalent encodings
77 included for side-by-side comparison (and listed below, separately).
81 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
82 | Encoding | 17 | 16 | 15 | 14 | 13 | 12 | 11:7 | 6 | 5:0 |
83 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
84 | P48-LD-type | rd[5] | rs1[5] | vitp7[6] | vd | vs1 | vitp7[5:0] | *Reserved* | 011111 |
85 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
86 | P48-ST-type |vitp7[6]| rs1[5] | rs2[5] | vs2 | vs1 | vitp7[5:0] | *Reserved* | 011111 |
87 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
88 | P48-R-type | rd[5] | rs1[5] | rs2[5] | vs2 | vs1 | vitp6 | *Reserved* | 011111 |
89 +---------------+--------+------------+------------+-----+------------+--------------------+------------+--------+
90 | P48-I-type | rd[5] | rs1[5] | vitp7[6] | vd | vs1 | vitp7[5:0] | *Reserved* | 011111 |
91 +---------------+--------+------------+------------+-----+------------+--------------------+------------+--------+
92 | P48-U-type | rd[5] | *Reserved* | *Reserved* | vd | *Reserved* | vitp6 | *Reserved* | 011111 |
93 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
94 | P48-FR-type | rd[5] | rs1[5] | rs2[5] | vs2 | vs1 | *Reserved* | vtp5 | *Reserved* | 011111 |
95 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
96 | P48-FI-type | rd[5] | rs1[5] | vitp7[6] | vd | vs1 | vitp7[5:0] | *Reserved* | 011111 |
97 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
98 | P48-FR4-type | rd[5] | rs1[5] | rs2[5] | vs2 | rs3[5] | vs3 [#fr4]_ | vtp5 | *Reserved* | 011111 |
99 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
101 .. [#fr4] Only vs2 and vs3 are included in the P48-FR4-type encoding because
102 there is not enough space for vs1 as well, and because it is more
103 useful to have a scalar argument for each of the multiplication and
104 addition portions of fmadd than to have two scalars on the
105 multiplication portion.
107 Table showing correspondance between P48-*-type and RV32-*-type. These are
108 bits 47:18 (RV32 shifted up by 16 bits):
110 +---------------+---------------+
112 +---------------+---------------+
113 | RV32 Encoding | 31:2 |
114 +---------------+---------------+
115 | P48-LD-type | RV32-I-type |
116 +---------------+---------------+
117 | P48-ST-type | RV32-S-Type |
118 +---------------+---------------+
119 | P48-R-type | RV32-R-Type |
120 +---------------+---------------+
121 | P48-I-type | RV32-I-Type |
122 +---------------+---------------+
123 | P48-U-type | RV32-U-Type |
124 +---------------+---------------+
125 | P48-FR-type | RV32-FR-Type |
126 +---------------+---------------+
127 | P48-FI-type | RV32-I-Type |
128 +---------------+---------------+
129 | P48-FR4-type | RV32-FR-type |
130 +---------------+---------------+
132 Table showing Standard RV32 encodings:
134 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
135 | Encoding | 31:27 | 26:25 | 24:20 | 19:15 | 14:12 | 11:7 | 6:2 | 1 | 0 |
136 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
137 | RV32-R-type + funct7 + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0] + opcode + 1 + 1 |
138 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
139 | RV32-S-type + imm[11:5] + rs2[4:0] + rs1[4:0] + funct3 | imm[4:0] + opcode + 1 + 1 |
140 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
141 | RV32-I-type + imm[11:0] + rs1[4:0] + funct3 | rd[4:0] + opcode + 1 + 1 |
142 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
143 | RV32-U-type + imm[31:12] | rd[4:0] + opcode + 1 + 1 |
144 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
145 | RV32-FR4-type + rs3[4:0] + fmt + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0] + opcode + 1 + 1 |
146 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
147 | RV32-FR-type + funct5 + fmt + rs2[4:0] + rs1[4:0] + rm | rd[4:0] + opcode + 1 + 1 |
148 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
150 64-bit Instruction Encodings
151 ============================
153 Where in the 48 bit format the prefix is "0b0011111" in bits 0 to 6, this is
154 now set to "0b0111111".
156 +---------------+---------------+--------------+-----------+
157 | 63:48 | 47:18 | 17:7 | 6:0 |
158 +---------------+---------------+--------------+-----------+
159 | 64 bit prefix | RV32[31:3] | P48[17:7] | 0b0111111 |
160 +---------------+---------------+--------------+-----------+
162 * The 64 bit prefix format is below
163 * Bits 18 to 47 contain bits 3 to 31 of a standard RV32 format
164 * Bits 7 to 17 contain bits 7 through 17 of the P48 format
165 * Bits 0 to 6 contain the standard RV 64-bit prefix 0b0111111
167 64 bit prefix format:
169 +--------------+-------+--------+--------+--------+--------+
170 | Encoding | 63 | 62 | 61 | 60 | 59:48 |
171 +--------------+-------+--------+--------+--------+--------+
172 | P64-LD-type | rd[6] | rs1[6] | | | VLtyp |
173 +--------------+-------+--------+--------+--------+--------+
174 | P64-ST-type | | rs1[6] | rs2[6] | | VLtyp |
175 +--------------+-------+--------+--------+--------+--------+
176 | P64-R-type | rd[6] | rs1[6] | rs2[6] | | VLtyp |
177 +--------------+-------+--------+--------+--------+--------+
178 | P64-I-type | rd[6] | rs1[6] | | | VLtyp |
179 +--------------+-------+--------+--------+--------+--------+
180 | P64-U-type | rd[6] | | | | VLtyp |
181 +--------------+-------+--------+--------+--------+--------+
182 | P64-FR-type | | rs1[6] | rs2[6] | | VLtyp |
183 +--------------+-------+--------+--------+--------+--------+
184 | P64-FI-type | rd[6] | rs1[6] | rs2[6] | | VLtyp |
185 +--------------+-------+--------+--------+--------+--------+
186 | P64-FR4-type | rd[6] | rs1[6] | rs2[6] | rs3[6] | VLtyp |
187 +--------------+-------+--------+--------+--------+--------+
189 The extra bit for src and dest registers provides the full range of
190 up to 128 registers, when combined with the extra bit from the 48 bit
191 prefix as well. VLtyp encodes how (whether) to set VL and MAXVL.
196 NOTE: VL and MVL below are modified (potentially damaging) and so is the STATE CSR. It is the responsibility of the programmer to ensure that modifications to STATE do not compromise loops or VLIW Group opetations, by saving and restoring the STATE CSR (if needed).
198 +-----------+-------------+--------------+----------+----------------------+
199 | VLtyp[11] | VLtyp[10:6] | VLtyp[5:1] | VLtyp[0] | comment |
200 +-----------+-------------+--------------+----------+----------------------+
201 | 0 | 000000 | 00000 | 0 | no change to VL/MVL |
202 +-----------+-------------+--------------+----------+----------------------+
203 | 0 | VLdest | VLEN | vlt | VL imm/reg mode (vlt)|
204 +-----------+-------------+--------------+----------+----------------------+
205 | 1 | VLdest | MVL+VL-immed | 0 | MVL+VL immed mode |
206 +-----------+-------------+--------------+----------+----------------------+
207 | 1 | VLdest | MVL-immed | 1 | MVL immed mode |
208 +-----------+-------------+--------------+----------+----------------------+
210 Note: when VLtyp is all zeros, neither VL nor MVL are changed.
212 Just as in the VLIW format, when bit 11 of VLtyp is zero:
214 * if vlt is zero, bits 1 to 5 specify the VLEN as a 5 bit immediate
215 (offset by 1: 0b00000 represents VL=1, 0b00001 represents VL=2 etc.)
216 * if vlt is 1, bits 1 to 5 specify the scalar (RV standard) register
217 from which VL is set. x0 is not permitted
218 * VL goes into the scalar register VLdest (if VLdest is not x0)
220 When bit 11 of VLtype is 1:
222 * if VLtyp[0] is zero, both MAXVL and VL are set to (imm+1). The same
223 value goes into the scalar register VLdest (if VLdest is not x0)
224 * if VLtyp[0] is 1, MAXVL is set to (imm+1).
225 VL will be truncated to within the new range (if VL was greater
226 than the new MAXVL). The new VL goes into the scalar register VLdest
227 (if VLdest is not x0).
229 This gives the option to set up VL in a "loop mode" (VLtype[11]=0) or
230 in a "one-off" mode (VLtype[11]=1) which sets both MVL and VL to the
231 same immediate value. This may be most useful for one-off Vectorised
232 operations such as LOAD-MULTI / STORE-MULTI, for saving and restoration
233 of large batches of registers in context-switches or function calls.
235 Note that VLtyp's VL and MVL are the same as the main Specification_ VL or MVL, and that loops will also alter srcoffs and destoffs. It is the programmer's responsibility to ensure that STATE is not compromised (e.g saved to a temp reg or to the stack).
237 Furthermore, the execution order and exception handling must be exactly the same as in the main spec.
239 vs#/vd Fields' Encoding
240 =======================
242 +--------+----------+----------------------------------------------------------+
243 | vs#/vd | Mnemonic | Meaning |
244 +========+==========+==========================================================+
245 | 0 | S | the rs#/rd field specifies a scalar (single sub-vector); |
246 | | | the rs#/rd field is zero-extended to get the actual |
247 | | | 7-bit register number |
248 +--------+----------+----------------------------------------------------------+
249 | 1 | V | the rs#/rd field specifies a vector; the rs#/rd field is |
250 | | | decoded using the `Vector Register Number Encoding`_ to |
251 | | | get the actual 7-bit register number |
252 +--------+----------+----------------------------------------------------------+
254 If a vs#/vd field is not present, it is as if it was present with a value that
255 is the bitwise-or of all present vs#/vd fields.
257 * scalar register numbers do NOT increment when allocated in the
258 hardware for-loop. the same scalar register number is handed
261 * vector register numbers *DO* increase when allocated in the
262 hardware for-loop. sequentially-increasing register data
263 is handed to sequential ALUs.
265 Vector Register Number Encoding
266 ===============================
268 For the 48 bit format, when vs#/vd is 1, the actual 7-bit register number is derived from the
269 corresponding 6-bit rs#/rd field:
271 +---------------------------------+
272 | Actual 7-bit register number |
273 +===========+=============+=======+
274 | Bit 6 | Bits 5:1 | Bit 0 |
275 +-----------+-------------+-------+
276 | rs#/rd[0] | rs#/rd[5:1] | 0 |
277 +-----------+-------------+-------+
279 For the 64 bit format, the 7 bit register is constructed from the 7 bit fields: bits 0 to 4 from the 32 bit RV Standard format, bit 5 from the 48 bit prefix and bit 6 from the 64 bit prefix. Thus in the 64 bit format the full range of up to 128 registers is directly available. This for both when either scalar or vector mode is set.
281 Load/Store Kind (lsk) Field Encoding
282 ====================================
284 +--------+-----+--------------------------------------------------------------------------------+
285 | vd/vs2 | vs1 | Meaning |
286 +========+=====+================================================================================+
287 | 0 | 0 | srcbase is scalar, LD/ST is pure scalar. |
288 +--------+-----+--------------------------------------------------------------------------------+
289 | 1 | 0 | srcbase is scalar, LD/ST is unit strided |
290 +--------+-----+--------------------------------------------------------------------------------+
291 | 0 | 1 | srcbase is a vector (gather/scatter aka array of srcbases). VSPLAT and VSELECT |
292 +--------+-----+--------------------------------------------------------------------------------+
293 | 1 | 1 | srcbase is a vector, LD/ST is a full vector LD/ST. |
294 +--------+-----+--------------------------------------------------------------------------------+
298 * A register strided LD/ST would require *5* registers. srcbase, vd/vs2, predicate 1, predicate 2 and the stride register.
299 * Complex strides may all be done with a general purpose vector of srcbases.
300 * Twin predication may be used even when vd/vs1 is a scalar, to give VSPLAT and VSELECT, because the hardware loop ends on the first occurrence of a 1 in the predicate when a predicate is applied to a scalar.
301 * Full vectorised gather/scatter is enabled when both registers are marked as vectorised, however unlike e.g Intel AVX512, twin predication can be applied.
303 Open question: RVV overloads the width field of LOAD-FP/STORE-FP using the bit 2 to indicate additional interpretation of the 11 bit immediate. Should this be considered?
306 Sub-Vector Length (svlen) Field Encoding
307 =======================================================
309 NOTE: svlen is the same as the main spec SUBVL, and modifies the STATE CSR. The same caveats apply to svlen as do to SUBVL.
311 Bitwidth, from VL's perspective, is a multiple of the elwidth times svlen. So within each loop of VL there are svlen sub-elements of elwidth in size, just like in a SIMD architecture. When svlen is set to 0b00 (indicating svlen=1) no such SIMD-like behaviour exists and the subvectoring is disabled.
313 Predicate bits do not apply to the individual sub-vector elements, they apply to the entire subvector group. This saves instructions on setup of the predicate.
315 +----------------+-------+
316 | svlen Encoding | Value |
317 +================+=======+
319 +----------------+-------+
321 +----------------+-------+
323 +----------------+-------+
325 +----------------+-------+
327 In independent standalone implementations that do not implement the main specification, the SUBVL CSR (svtyp=0b00) may be assumed to be 1.
329 Behaviour of operations that set svlen are identical to those of the main spec. See section on VLtyp, above.
331 Predication (pred) Field Encoding
332 =================================
334 +------+------------+--------------------+----------------------------------------+
335 | pred | Mnemonic | Predicate Register | Meaning |
336 +======+============+====================+========================================+
337 | 000 | *None* | *None* | The instruction is unpredicated |
338 +------+------------+--------------------+----------------------------------------+
339 | 001 | *Reserved* | *Reserved* | |
340 +------+------------+--------------------+----------------------------------------+
341 | 010 | !x9 | x9 (s1) | execute vector op[0..i] on x9[i] == 0 |
342 +------+------------+ +----------------------------------------+
343 | 011 | x9 | | execute vector op[0..i] on x9[i] == 1 |
344 +------+------------+--------------------+----------------------------------------+
345 | 100 | !x10 | x10 (a0) | execute vector op[0..i] on x10[i] == 0 |
346 +------+------------+ +----------------------------------------+
347 | 101 | x10 | | execute vector op[0..i] on x10[i] == 1 |
348 +------+------------+--------------------+----------------------------------------+
349 | 110 | !x11 | x11 (a1) | execute vector op[0..i] on x11[i] == 0 |
350 +------+------------+ +----------------------------------------+
351 | 111 | x11 | | execute vector op[0..i] on x11[i] == 1 |
352 +------+------------+--------------------+----------------------------------------+
354 Twin-predication (tpred) Field Encoding
355 =======================================
357 +-------+------------+--------------------+----------------------------------------------+
358 | tpred | Mnemonic | Predicate Register | Meaning |
359 +=======+============+====================+==============================================+
360 | 000 | *None* | *None* | The instruction is unpredicated |
361 +-------+------------+--------------------+----------------------------------------------+
362 | 001 | x9,off | src=x9, dest=none | src[0..i] uses x9[i], dest unpredicated |
363 +-------+------------+ +----------------------------------------------+
364 | 010 | off,x10 | src=none, dest=x10 | dest[0..i] uses x10[i], src unpredicated |
365 +-------+------------+ +----------------------------------------------+
366 | 011 | x9,10 | src=x9, dest=x10 | src[0..i] uses x9[i], dest[0..i] uses x10[i] |
367 +-------+------------+--------------------+----------------------------------------------+
368 | 100 | *None* | *RESERVED* | Instruction is unpredicated (TBD) |
369 +-------+------------+--------------------+----------------------------------------------+
370 | 101 | !x9,off | src=!x9, dest=none | |
371 +-------+------------+ +----------------------------------------------+
372 | 110 | off,!x10 | src=none, dest=!x10| |
373 +-------+------------+ +----------------------------------------------+
374 | 111 | !x9,!x10 | src=!x9, dest=!x10 | |
375 +-------+------------+--------------------+----------------------------------------------+
377 Integer Element Type (itype) Field Encoding
378 ===========================================
380 +------------+-------+--------------+--------------+-----------------+-------------------+
381 | Signedness | itype | Element Type | Mnemonic in | Mnemonic in FP | Meaning (INT may |
382 | [#sgn_def]_| | | Integer | Instructions | be un/signed, FP |
383 | [#sgn_def]_| | | Instructions | (such as fmv.x) | just re-sized |
384 +============+=======+==============+==============+=================+===================+
385 | Unsigned | 01 | u8 | BU | BU | Unsigned 8-bit |
386 | +-------+--------------+--------------+-----------------+-------------------+
387 | | 10 | u16 | HU | HU | Unsigned 16-bit |
388 | +-------+--------------+--------------+-----------------+-------------------+
389 | | 11 | u32 | WU | WU | Unsigned 32-bit |
390 | +-------+--------------+--------------+-----------------+-------------------+
391 | | 00 | uXLEN | WU/DU/QU | WU/LU/TU | Unsigned XLEN-bit |
392 +------------+-------+--------------+--------------+-----------------+-------------------+
393 | Signed | 01 | i8 | BS | BS | Signed 8-bit |
394 | +-------+--------------+--------------+-----------------+-------------------+
395 | | 10 | i16 | HS | HS | Signed 16-bit |
396 | +-------+--------------+--------------+-----------------+-------------------+
397 | | 11 | i32 | W | W | Signed 32-bit |
398 | +-------+--------------+--------------+-----------------+-------------------+
399 | | 00 | iXLEN | W/D/Q | W/L/T | Signed XLEN-bit |
400 +------------+-------+--------------+--------------+-----------------+-------------------+
402 .. [#sgn_def] Signedness is defined in `Signedness Decision Procedure`_
404 Note: vector mode is effectively a type-cast of the register file
405 as if it was a sequential array being typecast to typedef itype[]
406 (c syntax). The starting point of the "typecast" is the vector
409 Example: if itype=0b10 (u16), and rd is set to "vector", and
410 VL is set to 4, the 64-bit register at rd is subdivided into
411 *FOUR* 16-bit destination elements. It is *NOT* four
412 separate 64-bit destination registers (rd+0, rd+1, rd+2, rd+3)
413 that are sign-extended from the source width size out to 64-bit,
414 because that is itype=0b00 (uXLEN).
416 Note also: changing elwidth creates packed elements that, depending on VL, may create vectors that do not fit perfectly onto XLEM sized rehistry file boundaries. This does NOT result in the destruction of the MSBs of the last register written to at the end of a VL loop. More details on how to handle this are described in the main Specification_.
418 Signedness Decision Procedure
419 =============================
421 1. If the opcode field is either OP or OP-IMM, then
422 1. Signedness is Unsigned.
423 2. If the opcode field is either OP-32 or OP-IMM-32, then
424 1. Signedness is Signed.
425 3. If Signedness is encoded in a field of the base instruction, [#sign_enc]_ then
426 1. Signedness uses the encoded value.
428 1. Signedness is Unsigned.
430 .. [#sign_enc] Like in fcvt.d.l[u], but unlike in fmv.x.w, since there is no
433 Vector Type and Predication 5-bit (vtp5) Field Encoding
434 =======================================================
436 In the following table, X denotes a wildcard that is 0 or 1 and can be a
437 different value for every occurrence.
439 +-------+-----------+-----------+
440 | vtp5 | pred | svlen |
441 +=======+===========+===========+
442 | 1XXXX | vtp5[4:2] | vtp5[1:0] |
447 +-------+-----------+-----------+
448 | 001XX | *Reserved* |
449 +-------+-----------------------+
451 Vector Integer Type and Predication 6-bit (vitp6) Field Encoding
452 ================================================================
454 In the following table, X denotes a wildcard that is 0 or 1 and can be a
455 different value for every occurrence.
457 +--------+------------+---------+------------+------------+
458 | vitp6 | itype | pred[2] | pred[0:1] | svlen |
459 +========+============+=========+============+============+
460 | XX1XXX | vitp6[5:4] | 0 | vitp6[3:2] | vitp6[1:0] |
463 +--------+------------+---------+------------+------------+
464 | XX01XX | *Reserved* |
465 +--------+------------------------------------------------+
467 vitp7 field: only tpred
469 +---------+------------+----------+-------------+------------+
470 | vitp7 | itype | tpred[2] | tpred[0:1] | svlen |
471 +=========+============+==========+=============+============+
472 | XXXXXXX | vitp7[5:4] | vitp7[6] | vitp7[3:2] | vitp7[1:0] |
473 +---------+------------+----------+-------------+------------+
475 48-bit Instruction Encoding Decision Procedure
476 ==============================================
478 In the following decision procedure, *Reserved* means that there is not yet a
479 defined 48-bit instruction encoding for the base instruction.
481 1. If the base instruction is a load instruction, then
482 a. If the base instruction is an I-type instruction, then
483 1. The encoding is P48-LD-type.
485 1. The encoding is *Reserved*.
486 2. If the base instruction is a store instruction, then
487 a. If the base instruction is an S-type instruction, then
488 1. The encoding is P48-ST-type.
490 1. The encoding is *Reserved*.
491 3. If the base instruction is a SYSTEM instruction, then
492 a. The encoding is *Reserved*.
493 4. If the base instruction is an integer instruction, then
494 a. If the base instruction is an R-type instruction, then
495 1. The encoding is P48-R-type.
496 b. If the base instruction is an I-type instruction, then
497 1. The encoding is P48-I-type.
498 c. If the base instruction is an S-type instruction, then
499 1. The encoding is *Reserved*.
500 d. If the base instruction is an B-type instruction, then
501 1. The encoding is *Reserved*.
502 e. If the base instruction is an U-type instruction, then
503 1. The encoding is P48-U-type.
504 f. If the base instruction is an J-type instruction, then
505 1. The encoding is *Reserved*.
507 1. The encoding is *Reserved*.
508 5. If the base instruction is a floating-point instruction, then
509 a. If the base instruction is an R-type instruction, then
510 1. The encoding is P48-FR-type.
511 b. If the base instruction is an I-type instruction, then
512 1. The encoding is P48-FI-type.
513 c. If the base instruction is an S-type instruction, then
514 1. The encoding is *Reserved*.
515 d. If the base instruction is an B-type instruction, then
516 1. The encoding is *Reserved*.
517 e. If the base instruction is an U-type instruction, then
518 1. The encoding is *Reserved*.
519 f. If the base instruction is an J-type instruction, then
520 1. The encoding is *Reserved*.
521 g. If the base instruction is an R4-type instruction, then
522 1. The encoding is P48-FR4-type.
524 1. The encoding is *Reserved*.
526 a. The encoding is *Reserved*.
531 CSRs are the same as in the main Specification_, if associated functionality is implemented. They have the exact same meaning as in the main specification.
538 Associated SET and GET on the CSRs is exactly as in the main spec as well (including CSRRWI and CSRRW differences).
540 Additional Instructions
541 =======================
543 Add instructions to convert between integer types.
545 Add instructions to `swizzle`_ elements in sub-vectors. Note that the sub-vector
546 lengths of the source and destination won't necessarily match.
548 .. _swizzle: https://www.khronos.org/opengl/wiki/Data_Type_(GLSL)#Swizzling
550 Add instructions to transpose (2-4)x(2-4) element matrices.
552 Add instructions to insert or extract a sub-vector from a vector, with the index
553 allowed to be both immediate and from a register (*immediate can be covered partly
554 by twin-predication, register cannot: requires MV.X aka VSELECT*)
556 Add a register gather instruction (aka MV.X)
558 # Open questions <a name="questions"></a>
560 Confirmation needed as to whether subvector extraction can be covered by twin predication (it probably can, it is one of the many purposes it is for).
564 What is SUBVL and how does it work
568 SVorig goes to a lot of effort to make VL 1<= MAXVL and MAXVL 1..64 where both CSRs may be stored internally in only 6 bits.
570 Thus, CSRRWI can reach 1..32 for VL and MAXVL.
572 In addition, setting a hardware loop to zero turning instructions into NOPs, um, just branch over them, to start the first loop at the end, on the test for loop variable being zero, a la c "while do" instead of "do while".
574 Or, does it not matter that VL only goes up to 31 on a CSRRWI, and that it only goes to a max of 63 rather than 64?
578 Should these questions be moved to Discussion subpage
582 Is MV.X good enough a substitute for swizzle?
586 Is vectorised srcbase ok as a gather scatter and ok substitute for register stride? 5 dependency registers (reg stride being the 5th) is quite scary
590 Why are integer conversion instructions needed, when the main SV spec covers them by allowing elwidth to be set on both src and dest regs?
594 Why are the SETVL rules so complex? What is the reason, how are loops carried out?
598 With SUBVL (sub vector len) being both a CSR and also part of the 48/64 bit opcode, how does that work?
602 What are the interaction rules when a 48/64 prefix opcode has a rd/rs that already has a Vector Context for either predication or a register?
604 It would perhaps make sense (and for svlen as well) to make 48/64 isolated and unaffected by VLIW context, with the exception of VL/MVL.
606 MVL and VL should be modifiable by 64 bit prefix as they are global in nature.
608 Possible solution, svlen and VLtyp allowed to share STATE CSR however programmer becomes responsible for push and pop of state during use of a sequence of P48 and P64 ops.
projects / libreriscv.git / blob