simple_v_extension/sv_prefix_proposal.rst

   1 SimpleV Prefix (SVprefix) Proposal v0.2
   2 =======================================
   3
   4 This proposal is designed to be able to operate without SVcsr, but not to
   5 require the absence of SVcsr.
   6
   7 Conventions
   8 ===========
   9
  10 Conventions used in this document:
  11 - Bits are numbered starting from 0 at the LSB, so bit 3 is 1 in the integer 8.
  12 - Bit ranges are inclusive on both ends, so 5:3 means bits 5, 4, and 3.
  13
  14 Operations work on variable-length vectors of sub-vectors, where each sub-vector
  15 has a length *svlen*, and an element type *etype*. When the vectors are stored
  16 in registers, all elements are packed so that there is no padding in-between
  17 elements of the same vector. The number of bytes in a sub-vector, *svsz*, is the
  18 product of *svlen* and the element size in bytes.
  19
  20 Half-Precision Floating Point (FP16)
  21 ====================================
  22 If the F extension is supported, SVprefix adds support for FP16 in the
  23 base FP instructions by using 10 (H) in the floating-point format field *fmt*
  24 and using 001 (H) in the floating-point load/store *width* field.
  25
  26 Compressed Instructions
  27 =======================
  28 This proposal doesn't include any prefixed RVC instructions, instead, it will
  29 include 32-bit instructions that are compressed forms of SVprefix 48-bit
  30 instructions, in the same manner that RVC instructions are compressed forms of
  31 RVI instructions. The compressed instructions will be defined later by
  32 considering which 48-bit instructions are the most common.
  33
  34 48-bit Prefixed Instructions
  35 ============================
  36 All 48-bit prefixed instructions contain a 32-bit "base" instruction as the
  37 last 4 bytes. Since all 32-bit instructions have bits 1:0 set to 11, those bits
  38 are reused for additional encoding space in the 48-bit instructions.
  39
  40 64-bit Prefixed Instructions
  41 ============================
  42
  43 TODO.  Really need to resolve vitp7 by reducing lsk to 2 bits, or just use
  44 0b111111 as the prefix, then lsk can remain at 3 bits.
  45
  46 48-bit Instruction Encodings
  47 ============================
  48
  49 In the following table, *Reserved* entries must be zero.  RV32 equivalent encodings
  50 included for side-by-side comparison (and listed below, separately).
  51
  52 First, bits 17:0:
  53
  54 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  55 | Encoding      | 17     | 16         | 15         | 14  | 13         | 12          | 11:7 | 6          | 5:0    |
  56 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  57 | P48-LD-type   | rd[5]  | rs1[5]     | vitp7[6]   | vd  | vs1        | vitp7[5:0]         | *Reserved* | 011111 |
  58 +---------------+--------+------------+------------+--------------------------------+------+------------+--------+
  59 | P48-ST-type   |vitp7[6]| rs1[5]     | rs2[5]     | vs2 | vs1        | vitp7[5:0]         | *Reserved* | 011111 |
  60 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  61 | P48-R-type    | rd[5]  | rs1[5]     | rs2[5]     | vs2 | vs1        | vitp6              | *Reserved* | 011111 |
  62 +---------------+--------+------------+------------+-----+------------+--------------------+------------+--------+
  63 | P48-I-type    | rd[5]  | rs1[5]     | vitp7[6]   | vd  | vs1        | vitp7[5:0]         | *Reserved* | 011111 |
  64 +---------------+--------+------------+------------+-----+------------+--------------------+------------+--------+
  65 | P48-U-type    | rd[5]  | *Reserved* | *Reserved* | vd  | *Reserved* | vitp6              | *Reserved* | 011111 |
  66 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  67 | P48-FR-type   | rd[5]  | rs1[5]     | rs2[5]     | vs2 | vs1        | *Reserved*  | vtp5 | *Reserved* | 011111 |
  68 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  69 | P48-FI-type   | rd[5]  | rs1[5]     | vitp7[6]   | vd  | vs1        | vitp7[5:0]         | *Reserved* | 011111 |
  70 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  71 | P48-FR4-type  | rd[5]  | rs1[5]     | rs2[5]     | vs2 | rs3[5]     | vs3 [#fr4]_ | vtp5 | *Reserved* | 011111 |
  72 +---------------+--------+------------+------------+-----+------------+-------------+------+------------+--------+
  73
  74 .. [#fr4] Only vs2 and vs3 are included in the P48-FR4-type encoding because
  75           there is not enough space for vs1 as well, and because it is more
  76           useful to have a scalar argument for each of the multiplication and
  77           addition portions of fmadd than to have two scalars on the
  78           multiplication portion.
  79
  80 Table showing correspondance between P48-*-type and RV32-*-type.  These are
  81 bits 47:18 (RV32 shifted up by 16 bits):
  82
  83 +---------------+---------------+
  84 | Encoding      | 47:18         |
  85 +---------------+---------------+
  86 | RV32 Encoding | 31:2          |
  87 +---------------+---------------+
  88 | P48-LD-type   | RV32-I-type   |
  89 +---------------+---------------+
  90 | P48-ST-type   | RV32-S-Type   |
  91 +---------------+---------------+
  92 | P48-R-type    | RV32-R-Type   |
  93 +---------------+---------------+
  94 | P48-I-type    | RV32-I-Type   |
  95 +---------------+---------------+
  96 | P48-U-type    | RV32-U-Type   |
  97 +---------------+---------------+
  98 | P48-FR-type   | RV32-FR-Type  |
  99 +---------------+---------------+
 100 | P48-FI-type   | RV32-I-Type   |
 101 +---------------+---------------+
 102 | P48-FR4-type  | RV32-FR-type  |
 103 +---------------+---------------+
 104
 105 Separately, RV32 encodings:
 106
 107 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 108 | Encoding      | 31:27       | 26:25 | 24:20    | 19:15    | 14:12  | 11:7     | 6:2    | 1      | 0          |
 109 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 110 | RV32-R-type   +    funct7           + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0]  + opcode + 1      + 1          |
 111 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 112 | RV32-S-type   + imm[11:5]           + rs2[4:0] + rs1[4:0] + funct3 | imm[4:0] + opcode + 1      + 1          |
 113 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 114 | RV32-I-type   + imm[11:0]                      + rs1[4:0] + funct3 | rd[4:0]  + opcode + 1      + 1          |
 115 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 116 | RV32-U-type   + imm[31:12]                                         | rd[4:0]  + opcode + 1      + 1          |
 117 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 118 | RV32-FR4-type + rs3[4:0]    + fmt   + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0]  + opcode + 1      + 1          |
 119 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 120 | RV32-FR-type  + funct5      + fmt   + rs2[4:0] + rs1[4:0] + rm     | rd[4:0]  + opcode + 1      + 1          |
 121 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+------------+
 122
 123 64-bit Instruction Encodings
 124 ============================
 125
 126 These extend the 48-bit encodings with the following additional bits:
 127
 128 +--------------+-------+-------+--------+--------+--------+----------+
 129 | Encoding     | 63:58 | 57    | 56     | 55     | 54     | 53:48    |
 130 +--------------+-------+-------+--------+--------+--------+----------+
 131 | P64-LD-type  | VL    | rd[6] | rs1[6] |        |        | Vstart   |
 132 +--------------+-------+-------+--------+--------+--------+----------+
 133 | P64-ST-type  | VL    |       | rs1[6] | rs2[6] |        | Vstart   |
 134 +--------------+-------+-------+--------+--------+--------+----------+
 135 | P64-R-type   | VL    | rd[6] | rs1[6] | rs2[6] |        | Vstart   |
 136 +--------------+-------+-------+--------+--------+--------+----------+
 137 | P64-I-type   | VL    | rd[6] | rs1[6] |        |        | Vstart   |
 138 +--------------+-------+-------+--------+--------+--------+----------+
 139 | P64-U-type   | VL    | rd[6] |        |        |        | Vstart   |
 140 +--------------+-------+-------+--------+--------+--------+----------+
 141 | P64-FR-type  | VL    |       | rs1[6] | rs2[6] |        | Vstart   |
 142 +--------------+-------+-------+--------+--------+--------+----------+
 143 | P64-FI-type  | VL    | rd[6] | rs1[6] | rs2[6] |        | Vstart   |
 144 +--------------+-------+-------+--------+--------+--------+----------+
 145 | P64-FR4-type | VL    | rd[6] | rs1[6] | rs2[6] | rs3[6] | Vstart   |
 146 +--------------+-------+-------+--------+--------+--------+----------+
 147
 148 vs#/vd Fields' Encoding
 149 =======================
 150
 151 +--------+----------+----------------------------------------------------------+
 152 | vs#/vd | Mnemonic | Meaning                                                  |
 153 +========+==========+==========================================================+
 154 | 0      | S        | the rs#/rd field specifies a scalar (single sub-vector); |
 155 |        |          | the rs#/rd field is zero-extended to get the actual      |
 156 |        |          | 7-bit register number                                    |
 157 +--------+----------+----------------------------------------------------------+
 158 | 1      | V        | the rs#/rd field specifies a vector; the rs#/rd field is |
 159 |        |          | decoded using the `Vector Register Number Encoding`_ to  |
 160 |        |          | get the actual 7-bit register number                     |
 161 +--------+----------+----------------------------------------------------------+
 162
 163 If a vs#/vd field is not present, it is as if it was present with a value that
 164 is the bitwise-or of all present vs#/vd fields.
 165
 166 * scalar register numbers do NOT increment when allocated in the
 167   hardware for-loop.  the same scalar register number is handed
 168   to every ALU.
 169
 170 * vector register numbers *DO* increase when allocated in the
 171   hardware for-loop.  sequentially-increasing register data
 172   is handed to sequential ALUs.
 173
 174 Vector Register Number Encoding
 175 ===============================
 176
 177 When vs#/vd is 1, the actual 7-bit register number is derived from the
 178 corresponding 6-bit rs#/rd field:
 179
 180 +---------------------------------+
 181 | Actual 7-bit register number    |
 182 +===========+=============+=======+
 183 | Bit 6     | Bits 5:1    | Bit 0 |
 184 +-----------+-------------+-------+
 185 | rs#/rd[0] | rs#/rd[5:1] | 0     |
 186 +-----------+-------------+-------+
 187
 188 TODO: similar scheme for 64-bit encoding (incorporating extra bit rs#/rd[6] from 64-bit encoding)
 189
 190 Load/Store Kind (lsk) Field Encoding
 191 ====================================
 192
 193 +------+----------+------------+-----------------------------------------------------------------+
 194 | vd/vs2 | vs1  | Meaning                                                         |
 195 +======+==========+============+=================================================================+
 196 | 0      | 0   | srcbase is scalar, LD/ST is pure scalar.                                                      |
 197 +------+----------+------------+-----------------------------------------------------------------+
 198 | 1     | 0   | srcbase is scalar, LD/ST is unit strided |
 199 +------+----------+------------+-----------------------------------------------------------------+
 200 | 0     | 1   | srcbase is a vector (gather/scatter aka array of srcbases). VSPLAT and VSELECT |
 201 +------+----------+------------+-----------------------------------------------------------------+
 202 | 1     | 1        | srcbase is a vector, LD/ST is a full vector LD/ST. |
 203 +------+----------+------------+-----------------------------------------------------------------+
 204
 205 Notes:
 206
 207 * A register strided LD/ST would require *5* registers. srcbase, vd/vs2, predicate 1, predicate 2 and the stride register.
 208 * Complex strides may all be done with a general purpose vector of srcbases.
 209 * Twin predication may be used even when vd/vs1 is a scalar, to give VSPLAT and VSELECT, because the hardware loop ends on the first occurrence of a 1 in the predicate when a predicate is applied to a scalar.
 210 * Full vectorised gather/scatter is enabled when both registers are marked as vectorised, however unlike e.g Intel AVX512, twin predication can be applied.
 211
 212 Open question: RVV overloads the width field of LOAD-FP/STORE-FP using the bit 2 to indicate additional interpretation of the 11 bit immediate. Should this be considered?
 213
 214
 215 Sub-Vector Length (svlen) Field Encoding
 216 =======================================================
 217
 218 +----------------+-------+
 219 | svlen Encoding | Value |
 220 +================+=======+
 221 | 00             | 4     |
 222 +----------------+-------+
 223 | 01             | 1     |
 224 +----------------+-------+
 225 | 10             | 2     |
 226 +----------------+-------+
 227 | 11             | 3     |
 228 +----------------+-------+
 229
 230 Predication (pred) Field Encoding
 231 =================================
 232
 233 +------+------------+--------------------+----------------------------------------+
 234 | pred | Mnemonic   | Predicate Register | Meaning                                |
 235 +======+============+====================+========================================+
 236 | 000  | *None*     | *None*             | The instruction is unpredicated        |
 237 +------+------------+--------------------+----------------------------------------+
 238 | 001  | *Reserved* | *Reserved*         |                                        |
 239 +------+------------+--------------------+----------------------------------------+
 240 | 010  | !x9        | x9 (s1)            | execute vector op[0..i] on x9[i] == 0  |
 241 +------+------------+                    +----------------------------------------+
 242 | 011  | x9         |                    | execute vector op[0..i] on x9[i] == 1  |
 243 +------+------------+--------------------+----------------------------------------+
 244 | 100  | !x10       | x10 (a0)           | execute vector op[0..i] on x10[i] == 0 |
 245 +------+------------+                    +----------------------------------------+
 246 | 101  | x10        |                    | execute vector op[0..i] on x10[i] == 1 |
 247 +------+------------+--------------------+----------------------------------------+
 248 | 110  | !x11       | x11 (a1)           | execute vector op[0..i] on x11[i] == 0 |
 249 +------+------------+                    +----------------------------------------+
 250 | 111  | x11        |                    | execute vector op[0..i] on x11[i] == 1 |
 251 +------+------------+--------------------+----------------------------------------+
 252
 253 Twin-predication (tpred) Field Encoding
 254 =======================================
 255
 256 +-------+------------+--------------------+----------------------------------------------+
 257 | tpred | Mnemonic   | Predicate Register | Meaning                                      |
 258 +=======+============+====================+==============================================+
 259 | 000   | *None*     | *None*             | The instruction is unpredicated              |
 260 +-------+------------+--------------------+----------------------------------------------+
 261 | 001   | x9,off     | src=x9, dest=none  | src[0..i] uses x9[i], dest unpredicated      |
 262 +-------+------------+                    +----------------------------------------------+
 263 | 010   | off,x10    | src=none, dest=x10 | dest[0..i] uses x10[i], src unpredicated     |
 264 +-------+------------+                    +----------------------------------------------+
 265 | 011   | x9,10      | src=x9, dest=x10   | src[0..i] uses x9[i], dest[0..i] uses x10[i] |
 266 +-------+------------+--------------------+----------------------------------------------+
 267 | 100   | *None*     | *RESERVED*         | Instruction is unpredicated (TBD)            |
 268 +-------+------------+--------------------+----------------------------------------------+
 269 | 101   | !x9,off    | src=!x9, dest=none |                                              |
 270 +-------+------------+                    +----------------------------------------------+
 271 | 110   | off,!x10   | src=none, dest=!x10|                                              |
 272 +-------+------------+                    +----------------------------------------------+
 273 | 111   | !x9,!x10   | src=!x9, dest=!x10 |                                              |
 274 +-------+------------+--------------------+----------------------------------------------+
 275
 276 Integer Element Type (itype) Field Encoding
 277 ===========================================
 278
 279 +------------+-------+--------------+--------------+-----------------+-------------------+
 280 | Signedness | itype | Element Type | Mnemonic in  | Mnemonic in FP  | Meaning (INT may  |
 281 | [#sgn_def]_|       |              | Integer      | Instructions    | be un/signed, FP  |
 282 | [#sgn_def]_|       |              | Instructions | (such as fmv.x) | just re-sized     |
 283 +============+=======+==============+==============+=================+===================+
 284 | Unsigned   | 00    | u8           | BU           | BU              | Unsigned 8-bit    |
 285 |            +-------+--------------+--------------+-----------------+-------------------+
 286 |            | 01    | u16          | HU           | HU              | Unsigned 16-bit   |
 287 |            +-------+--------------+--------------+-----------------+-------------------+
 288 |            | 10    | u32          | WU           | WU              | Unsigned 32-bit   |
 289 |            +-------+--------------+--------------+-----------------+-------------------+
 290 |            | 11    | uXLEN        | WU/DU/QU     | WU/LU/TU        | Unsigned XLEN-bit |
 291 +------------+-------+--------------+--------------+-----------------+-------------------+
 292 | Signed     | 00    | i8           | BS           | BS              | Signed 8-bit      |
 293 |            +-------+--------------+--------------+-----------------+-------------------+
 294 |            | 01    | i16          | HS           | HS              | Signed 16-bit     |
 295 |            +-------+--------------+--------------+-----------------+-------------------+
 296 |            | 10    | i32          | W            | W               | Signed 32-bit     |
 297 |            +-------+--------------+--------------+-----------------+-------------------+
 298 |            | 11    | iXLEN        | W/D/Q        | W/L/T           | Signed XLEN-bit   |
 299 +------------+-------+--------------+--------------+-----------------+-------------------+
 300
 301 .. [#sgn_def] Signedness is defined in `Signedness Decision Procedure`_
 302
 303 Note: vector mode is effectively a type-cast of the register file
 304 as if it was a sequential array being typecast to typedef itype[]
 305 (c syntax).  The starting point of the "typecast" is the vector
 306 register rs#/rd.
 307
 308 Example: if itype=0b01 (u16), and rd is set to "vector", and
 309 VL is set to 4, the 64-bit register at rd is subdivided into
 310 *FOUR* 16-bit destination elements.  It is *NOT* four
 311 separate 64-bit destination registers (rd+0, rd+1, rd+2, rd+3)
 312 that are sign-extended from the source width size out to 64-bit,
 313 because that is itype=0b11 (uXLEN).
 314
 315 Signedness Decision Procedure
 316 =============================
 317
 318 1. If the opcode field is either OP or OP-IMM, then
 319     1. Signedness is Unsigned.
 320 2. If the opcode field is either OP-32 or OP-IMM-32, then
 321     1. Signedness is Signed.
 322 3. If Signedness is encoded in a field of the base instruction, [#sign_enc]_ then
 323     1. Signedness uses the encoded value.
 324 4. Otherwise,
 325     1. Signedness is Unsigned.
 326
 327 .. [#sign_enc] Like in fcvt.d.l[u], but unlike in fmv.x.w, since there is no
 328                fmv.x.wu
 329
 330 Vector Type and Predication 5-bit (vtp5) Field Encoding
 331 =======================================================
 332
 333 In the following table, X denotes a wildcard that is 0 or 1 and can be a
 334 different value for every occurrence.
 335
 336 +-------+-----------+-----------+
 337 | vtp5  | pred      | svlen     |
 338 +=======+===========+===========+
 339 | 1XXXX | vtp5[4:2] | vtp5[1:0] |
 340 +-------+           |           |
 341 | 01XXX |           |           |
 342 +-------+           |           |
 343 | 000XX |           |           |
 344 +-------+-----------+-----------+
 345 | 001XX | *Reserved*            |
 346 +-------+-----------------------+
 347
 348 Vector Integer Type and Predication 6-bit (vitp6) Field Encoding
 349 ================================================================
 350
 351 In the following table, X denotes a wildcard that is 0 or 1 and can be a
 352 different value for every occurrence.
 353
 354 +--------+------------+---------+------------+------------+
 355 | vitp6  | itype      | pred[2] | pred[0:1]  | svlen      |
 356 +========+============+=========+============+============+
 357 | XX1XXX | vitp6[5:4] | 0       | vitp6[3:2] | vitp6[1:0] |
 358 +--------+            |         |            |            |
 359 | XX00XX |            |         |            |            |
 360 +--------+------------+---------+------------+------------+
 361 | XX01XX | *Reserved*                                     |
 362 +--------+------------------------------------------------+
 363
 364 vitp7 field: only tpred=
 365
 366 +---------+------------+----------+-------------+------------+
 367 | vitp7   | itype      | tpred[2] | tpred[0:1]  | svlen      |
 368 +=========+============+==========+=============+============+
 369 | XXXXXXX | vitp7[5:4] | vitp7[6] | vitp7[3:2]  | vitp7[1:0] |
 370 +---------+------------+----------+-------------+------------+
 371
 372 48-bit Instruction Encoding Decision Procedure
 373 ==============================================
 374
 375 In the following decision procedure, *Reserved* means that there is not yet a
 376 defined 48-bit instruction encoding for the base instruction.
 377
 378 1. If the base instruction is a load instruction, then
 379     a. If the base instruction is an I-type instruction, then
 380         1. The encoding is P48-LD-type.
 381     b. Otherwise
 382         1. The encoding is *Reserved*.
 383 2. If the base instruction is a store instruction, then
 384     a. If the base instruction is an S-type instruction, then
 385         1. The encoding is P48-ST-type.
 386     b. Otherwise
 387         1. The encoding is *Reserved*.
 388 3. If the base instruction is a SYSTEM instruction, then
 389     a. The encoding is *Reserved*.
 390 4. If the base instruction is an integer instruction, then
 391     a. If the base instruction is an R-type instruction, then
 392         1. The encoding is P48-R-type.
 393     b. If the base instruction is an I-type instruction, then
 394         1. The encoding is P48-I-type.
 395     c. If the base instruction is an S-type instruction, then
 396         1. The encoding is *Reserved*.
 397     d. If the base instruction is an B-type instruction, then
 398         1. The encoding is *Reserved*.
 399     e. If the base instruction is an U-type instruction, then
 400         1. The encoding is P48-U-type.
 401     f. If the base instruction is an J-type instruction, then
 402         1. The encoding is *Reserved*.
 403     g. Otherwise
 404         1. The encoding is *Reserved*.
 405 5. If the base instruction is a floating-point instruction, then
 406     a. If the base instruction is an R-type instruction, then
 407         1. The encoding is P48-FR-type.
 408     b. If the base instruction is an I-type instruction, then
 409         1. The encoding is P48-FI-type.
 410     c. If the base instruction is an S-type instruction, then
 411         1. The encoding is *Reserved*.
 412     d. If the base instruction is an B-type instruction, then
 413         1. The encoding is *Reserved*.
 414     e. If the base instruction is an U-type instruction, then
 415         1. The encoding is *Reserved*.
 416     f. If the base instruction is an J-type instruction, then
 417         1. The encoding is *Reserved*.
 418     g. If the base instruction is an R4-type instruction, then
 419         1. The encoding is P48-FR4-type.
 420     h. Otherwise
 421         1. The encoding is *Reserved*.
 422 6. Otherwise
 423     a. The encoding is *Reserved*.
 424
 425 CSR Registers
 426 =============
 427
 428 +--------+-----------------+---------------------------------------------------+
 429 | Name   | Legal Values    | Meaning                                           |
 430 +========+=================+===================================================+
 431 | VL     | 0 <= VL <= XLEN | Vector Length. The number of sub-vectors operated |
 432 |        |                 | on by vector instructions.                        |
 433 +--------+-----------------+---------------------------------------------------+
 434 | Vstart | 0 <= VL < XLEN  | The sub-vector index to start execution at.       |
 435 |        |                 | Successful completion of all elements in a vector |
 436 |        |                 | instruction sets Vstart to 0. Set to the index of |
 437 |        |                 | the failing sub-vector when a vector instruction  |
 438 |        |                 | traps.  Used to resume execution of vector        |
 439 |        |                 | instructions after a trap. Is *NOT* "slow"        |
 440 +--------+-----------------+---------------------------------------------------+
 441
 442 SetVL
 443 =====
 444
 445 setvl rd, rs1, imm
 446
 447 imm is the amount of space allocated from the register file by the compiler.
 448
 449 Pseudocode:
 450
 451 1. Trap if imm > XLEN.
 452 2. If rs1 is x0, then
 453     1. Set VL to imm.
 454 3. Else If regs[rs1] > 2 * imm, then
 455     1. Set VL to XLEN.
 456 4. Else If regs[rs1] > imm, then
 457     1. Set VL to regs[rs1] / 2 rounded down.
 458 5. Otherwise,
 459     1. Set VL to regs[rs1].
 460 6. Set regs[rd] to VL.
 461
 462 Additional Instructions
 463 =======================
 464
 465 Add instructions to convert between integer types.
 466
 467 Add instructions to `swizzle`_ elements in sub-vectors. Note that the sub-vector
 468 lengths of the source and destination won't necessarily match.
 469
 470 .. _swizzle: https://www.khronos.org/opengl/wiki/Data_Type_(GLSL)#Swizzling
 471
 472 Add instructions to transpose (2-4)x(2-4) element matrices.
 473
 474 Add instructions to insert or extract a sub-vector from a vector, with the index
 475 allowed to be both immediate and from a register (*immediate can be covered partly
 476 by twin-predication, register cannot: requires MV.X aka VSELECT*)
 477
 478 Add a register gather instruction (*NOT NEEDED*)
 479
 480 VSELECT instruction (or mechanism) is needed (aka MV.X)