simple_v_extension/sv_prefix_proposal.rst

   1 SimpleV Prefix (SVprefix) Proposal v0.3
   2 =======================================
   3
   4 * Copyright (c) Jacob Lifshay, 2019
   5 * Copyright (c) Luke Kenneth Casson Leighton, 2019
   6
   7 This proposal is designed to be able to operate without SVorig, but not to
   8 require the absence of SVorig. See Specification_.
   9
  10 Principle: SVprefix embeds (unmodified) RVC and 32-bit scalar opcodes
  11 into 32, 48 and 64 bit RV formats, to provide Vectorisation context
  12 on a per-instruction basis.
  13
  14 .. _Specification: http://libre-riscv.org/simple_v_extension/specification/
  15
  16 .. contents::
  17
  18 Conventions
  19 ===========
  20
  21 Conventions used in this document:
  22
  23 * Bits are numbered starting from 0 at the LSB, so bit 3 is 1 in the integer 8.
  24 * Bit ranges are inclusive on both ends, so 5:3 means bits 5, 4, and 3.
  25 * Operations work on variable-length vectors of sub-vectors up to *VL*
  26   in length, where each sub-vector has a length *svlen*, and *svlen*
  27   elements of type *etype*.
  28 * The actual total number of elements is therefore *svlen* times *VL*.
  29 * When the vectors are stored in registers, all elements are packed so
  30   that there is no padding in-between elements of the same vector.
  31 * The register file itself is thus best viewed as a byte-level SRAM that
  32   is typecast to an array of *etypes*
  33 * The number of bytes in a sub-vector, *svsz*, is the product of *svlen*
  34   and the element size in bytes.
  35
  36 Options
  37 =======
  38
  39 The following partial / full implementation options are possible:
  40
  41 * SVPrefix augments the main Specification_
  42 * SVPregix operates independently, without the main spec VL (and MVL)
  43   CSRs (in any priv level)
  44 * SVPrefix operates independently, without the main spec SUBVL CSRs
  45   (in any priv level)
  46 * SVPrefix has no support for VL (or MVL) overrides in the 64 bit
  47   instruction format (VLtyp=0 as the only legal permitted value)
  48 * SVPrefix has no support for svlen overrides in either the 48 or 64
  49   bit instruction format either (svlen=0 as the only legal permitted value).
  50
  51 All permutations of the above options are permitted, and the UNIX
  52 platform must raise illegal instruction exceptions on implementations
  53 that do not support each option.  For example, an implementation that
  54 has no support for VLtyp that sees an opcode with a nonzero VLtyp must
  55 raise an illegal instruction exception.
  56
  57 Note that SVPrefix (VLtyp and svlen) and the main spec share (modify) the
  58 STATE CSR. P48 and P64 opcodes must **NOT** set VLtyp or svlen inside
  59 loops that also use VL or SUBVL. Doing so will result in undefined
  60 behaviour, as STATE will be affected by doing so.
  61
  62 However, using VLtyp or svlen in standalone operations, or pushing (and
  63 restoring) the contents of the STATE CSR to the stack, or just storing
  64 its contents in a temporary register whilst executing a sequence of P48
  65 or P64 opcodes, is perfectly fine.
  66
  67 If the main Specification_ CSRs are to be supported, the STATE, VL, MVL
  68 and SUBVL CSRs all operate according to the main specification. Under
  69 the options above, hypothetically an implementor could choose not to
  70 support setting of VL, MVL or SUBVL (only allowing them to be set to
  71 a value of 1). Under such circumstances, where *neither* VL/MVL *nor*
  72 SUBVL are supported, STATE would then not be required either.
  73
  74 If however support for SUBVL is to be provided, storing of the sub-vector
  75 offsets and SUBVL itself (and context switching of the same) in the
  76 STATE CSRs are mandatory.
  77
  78 Likewise if support for VL is to be provided, storing of VL, MVL and the
  79 dest and src offsets (and context switching of the same) in the STATE
  80 CSRs are mandatory.
  81
  82
  83 Half-Precision Floating Point (FP16)
  84 ====================================
  85
  86 If the F extension is supported, SVprefix adds support for FP16 in the
  87 base FP instructions by using 10 (H) in the floating-point format field
  88 *fmt* and using 001 (H) in the floating-point load/store *width* field.
  89
  90 Compressed Instructions
  91 =======================
  92
  93 This proposal does not include any prefixed RVC instructions, instead,
  94 it will include 32-bit instructions that are compressed forms of
  95 SVprefix 48-bit instructions, in the same manner that RVC instructions
  96 are compressed forms of RVI instructions. The compressed instructions
  97 will be defined later by considering which 48-bit instructions are the
  98 most common.
  99
 100 48-bit Prefixed Instructions
 101 ============================
 102
 103 All 48-bit prefixed instructions contain a 32-bit "base" instruction as
 104 the last 4 bytes. Since all 32-bit instructions have bits 1:0 set to
 105 11, those bits are reused for additional encoding space in the 48-bit
 106 instructions.
 107
 108 64-bit Prefixed Instructions
 109 ============================
 110
 111 The 48 bit format is further extended with the full 128-bit range on all
 112 source and destination registers, and the option to set both VL and MVL
 113 is provided.
 114
 115 48-bit Instruction Encodings
 116 ============================
 117
 118 In the following table, *Rsvd* (reserved) entries must be zero.  RV32 equivalent
 119 encodings included for side-by-side comparison (and listed below,
 120 separately).
 121
 122 First, bits 17:0:
 123
 124 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 125 | Encoding      | 17     | 16     | 15       | 14  | 13     | 12          | 11:7 | 6      | 5:0    |
 126 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 127 | P48-LD-type   | rd[5]  | rs1[5] | vitp7[6] | vd  | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
 128 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 129 | P48-ST-type   |vitp7[6]| rs1[5] | rs2[5]   | vs2 | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
 130 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 131 | P48-R-type    | rd[5]  | rs1[5] | rs2[5]   | vs2 | vs1    | vitp6              | *Rsvd* | 011111 |
 132 +---------------+--------+--------+----------+-----+--------+--------------------+--------+--------+
 133 | P48-I-type    | rd[5]  | rs1[5] | vitp7[6] | vd  | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
 134 +---------------+--------+--------+----------+-----+--------+--------------------+--------+--------+
 135 | P48-U-type    | rd[5]  | *Rsvd* | *Rsvd*   | vd  | *Rsvd* | vitp6              | *Rsvd* | 011111 |
 136 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 137 | P48-FR-type   | rd[5]  | rs1[5] | rs2[5]   | vs2 | vs1    | *Rsvd*      | vtp5 | *Rsvd* | 011111 |
 138 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 139 | P48-FI-type   | rd[5]  | rs1[5] | vitp7[6] | vd  | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
 140 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 141 | P48-FR4-type  | rd[5]  | rs1[5] | rs2[5]   | vs2 | rs3[5] | vs3 [#fr4]_ | vtp5 | *Rsvd* | 011111 |
 142 +---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 143
 144 .. [#fr4] Only vs2 and vs3 are included in the P48-FR4-type encoding
 145           because there is not enough space for vs1 as well, and because
 146           it is more useful to have a scalar argument for each of the
 147           multiplication and addition portions of fmadd than to have
 148           two scalars on the multiplication portion.
 149
 150 Table showing correspondance between P48-*-type and RV32-*-type.
 151 These are bits 47:18 (RV32 shifted up by 16 bits):
 152
 153 +---------------+---------------+
 154 | Encoding      | 47:18         |
 155 +---------------+---------------+
 156 | RV32 Encoding | 31:2          |
 157 +---------------+---------------+
 158 | P48-LD-type   | RV32-I-type   |
 159 +---------------+---------------+
 160 | P48-ST-type   | RV32-S-Type   |
 161 +---------------+---------------+
 162 | P48-R-type    | RV32-R-Type   |
 163 +---------------+---------------+
 164 | P48-I-type    | RV32-I-Type   |
 165 +---------------+---------------+
 166 | P48-U-type    | RV32-U-Type   |
 167 +---------------+---------------+
 168 | P48-FR-type   | RV32-FR-Type  |
 169 +---------------+---------------+
 170 | P48-FI-type   | RV32-I-Type   |
 171 +---------------+---------------+
 172 | P48-FR4-type  | RV32-FR4-type |
 173 +---------------+---------------+
 174
 175 Table showing Standard RV32 encodings:
 176
 177 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 178 | Encoding      | 31:27       | 26:25 | 24:20    | 19:15    | 14:12  | 11:7     | 6:2    | 1:0    |
 179 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 180 | RV32-R-type   +    funct7           + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0]  + opcode + 0b11   |
 181 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 182 | RV32-S-type   + imm[11:5]           + rs2[4:0] + rs1[4:0] + funct3 | imm[4:0] + opcode + 0b11   |
 183 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 184 | RV32-I-type   + imm[11:0]                      + rs1[4:0] + funct3 | rd[4:0]  + opcode + 0b11   |
 185 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 186 | RV32-U-type   + imm[31:12]                                         | rd[4:0]  + opcode + 0b11   |
 187 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 188 | RV32-FR4-type + rs3[4:0]    + fmt   + rs2[4:0] + rs1[4:0] + funct3 | rd[4:0]  + opcode + 0b11   |
 189 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 190 | RV32-FR-type  + funct5      + fmt   + rs2[4:0] + rs1[4:0] + rm     | rd[4:0]  + opcode + 0b11   |
 191 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 192
 193 64-bit Instruction Encodings
 194 ============================
 195
 196 Where in the 48 bit format the prefix is "0b0011111" in bits 0 to 6,
 197 this is now set to "0b0111111".
 198
 199 +---------------+---------------+--------------+-----------+
 200 | 63:48         | 47:18         | 17:7         | 6:0       |
 201 +---------------+---------------+--------------+-----------+
 202 | 64 bit prefix | RV32[31:3]    | P48[17:7]    | 0b0111111 |
 203 +---------------+---------------+--------------+-----------+
 204
 205 * The 64 bit prefix format is below
 206 * Bits 18 to 47 contain bits 3 to 31 of a standard RV32 format
 207 * Bits 7 to 17 contain bits 7 through 17 of the P48 format
 208 * Bits 0 to 6 contain the standard RV 64-bit prefix 0b0111111
 209
 210 64 bit prefix format:
 211
 212 +--------------+-------+--------+--------+--------+--------+
 213 | Encoding     | 63    | 62     | 61     | 60     | 59:48  |
 214 +--------------+-------+--------+--------+--------+--------+
 215 | P64-LD-type  | rd[6] | rs1[6] |        | *Rsvd* | VLtyp  |
 216 +--------------+-------+--------+--------+--------+--------+
 217 | P64-ST-type  |       | rs1[6] | rs2[6] | *Rsvd* | VLtyp  |
 218 +--------------+-------+--------+--------+--------+--------+
 219 | P64-R-type   | rd[6] | rs1[6] | rs2[6] | *Rsvd* | VLtyp  |
 220 +--------------+-------+--------+--------+--------+--------+
 221 | P64-I-type   | rd[6] | rs1[6] |        | *Rsvd* | VLtyp  |
 222 +--------------+-------+--------+--------+--------+--------+
 223 | P64-U-type   | rd[6] |        |        | *Rsvd* | VLtyp  |
 224 +--------------+-------+--------+--------+--------+--------+
 225 | P64-FR-type  |       | rs1[6] | rs2[6] | *Rsvd* | VLtyp  |
 226 +--------------+-------+--------+--------+--------+--------+
 227 | P64-FI-type  | rd[6] | rs1[6] | rs2[6] | *Rsvd* | VLtyp  |
 228 +--------------+-------+--------+--------+--------+--------+
 229 | P64-FR4-type | rd[6] | rs1[6] | rs2[6] | rs3[6] | VLtyp  |
 230 +--------------+-------+--------+--------+--------+--------+
 231
 232 The extra bit for src and dest registers provides the full range of
 233 up to 128 registers, when combined with the extra bit from the 48 bit
 234 prefix as well.  VLtyp encodes how (whether) to set VL and MAXVL.
 235
 236 VLtyp field encoding
 237 ====================
 238
 239 NOTE: VL and MVL below are modified (potentially damaging) and so is
 240 the STATE CSR. It is the responsibility of the programmer to ensure that
 241 modifications to STATE do not compromise loops or VBLOCK Group operations,
 242 by saving and restoring the STATE CSR (if needed).
 243
 244 +-----------+-------------+--------------+----------+----------------------+
 245 | VLtyp[11] | VLtyp[10:6] | VLtyp[5:1]   | VLtyp[0] | comment              |
 246 +-----------+-------------+--------------+----------+----------------------+
 247 | 0         |  00000      | 00000        |  0       | no change to VL/MVL  |
 248 +-----------+-------------+--------------+----------+----------------------+
 249 | 0         |  VLdest     | VLEN         |  vlt     | VL imm/reg mode (vlt)|
 250 +-----------+-------------+--------------+----------+----------------------+
 251 | 1         |  VLdest     | MVL+VL-immed | 0        | MVL+VL immed mode    |
 252 +-----------+-------------+--------------+----------+----------------------+
 253 | 1         |  VLdest     |  MVL-immed   | 1        | MVL immed mode       |
 254 +-----------+-------------+--------------+----------+----------------------+
 255
 256 Note: when VLtyp is all zeros, neither VL nor MVL are changed.
 257
 258 Just as in the VBLOCK format, when bit 11 of VLtyp is zero:
 259
 260 * if vlt is zero, bits 1 to 5 specify the VLEN as a 5 bit immediate
 261   (offset by 1: 0b00000 represents VL=1, 0b00001 represents VL=2 etc.)
 262 * if vlt is 1, bits 1 to 5 specify the scalar (RV standard) register
 263   from which VL is set.  x0 is not permitted
 264 * VL goes into the scalar register VLdest (if VLdest is not x0)
 265
 266 When bit 11 of VLtype is 1:
 267
 268 * if VLtyp[0] is zero, both MAXVL and VL are set to (imm+1).  The same
 269   value goes into the scalar register VLdest (if VLdest is not x0)
 270 * if VLtyp[0] is 1, MAXVL is set to (imm+1).
 271   VL will be truncated to within the new range (if VL was greater
 272   than the new MAXVL).  The new VL goes into the scalar register VLdest
 273   (if VLdest is not x0).
 274
 275 This gives the option to set up VL in a "loop mode" (VLtype[11]=0) or
 276 in a "one-off" mode (VLtype[11]=1) which sets both MVL and VL to the
 277 same immediate value.  This may be most useful for one-off Vectorised
 278 operations such as LOAD-MULTI / STORE-MULTI, for saving and restoration
 279 of large batches of registers in context-switches or function calls.
 280
 281 Note that VLtyp's VL and MVL are the same as the main Specification_
 282 VL or MVL, and that loops will also alter srcoffs and destoffs. It is
 283 the programmer's responsibility to ensure that STATE is not compromised
 284 (e.g saved to a temp reg or to the stack).
 285
 286 Furthermore, the execution order and exception handling must be exactly
 287 the same as in the main spec.
 288
 289 vs#/vd Fields' Encoding
 290 =======================
 291
 292 +--------+----------+----------------------------------------------------------+
 293 | vs#/vd | Mnemonic | Meaning                                                  |
 294 +========+==========+==========================================================+
 295 | 0      | S        | the rs#/rd field specifies a scalar (single sub-vector); |
 296 |        |          | the rs#/rd field is zero-extended to get the actual      |
 297 |        |          | 7-bit register number                                    |
 298 +--------+----------+----------------------------------------------------------+
 299 | 1      | V        | the rs#/rd field specifies a vector; the rs#/rd field is |
 300 |        |          | decoded using the `Vector Register Number Encoding`_ to  |
 301 |        |          | get the actual 7-bit register number                     |
 302 +--------+----------+----------------------------------------------------------+
 303
 304 If a vs#/vd field is not present, it is as if it was present with a value that
 305 is the bitwise-or of all present vs#/vd fields.
 306
 307 * scalar register numbers do NOT increment when allocated in the
 308   hardware for-loop.  the same scalar register number is handed
 309   to every ALU.
 310
 311 * vector register numbers *DO* increase when allocated in the
 312   hardware for-loop.  sequentially-increasing register data
 313   is handed to sequential ALUs.
 314
 315 Vector Register Number Encoding
 316 ===============================
 317
 318 For the 48 bit format, when vs#/vd is 1, the actual 7-bit register number
 319 is derived from the corresponding 6-bit rs#/rd field:
 320
 321 +---------------------------------+
 322 | Actual 7-bit register number    |
 323 +===========+=============+=======+
 324 | Bit 6     | Bits 5:1    | Bit 0 |
 325 +-----------+-------------+-------+
 326 | rs#/rd[0] | rs#/rd[5:1] | 0     |
 327 +-----------+-------------+-------+
 328
 329 For the 64 bit format, the 7 bit register is constructed from the 7 bit
 330 fields: bits 0 to 4 from the 32 bit RV Standard format, bit 5 from the 48
 331 bit prefix and bit 6 from the 64 bit prefix.  Thus in the 64 bit format
 332 the full range of up to 128 registers is directly available. This for
 333 both when either scalar or vector mode is set.
 334
 335 Load/Store Kind (lsk) Field Encoding
 336 ====================================
 337
 338 +--------+-----+--------------------------------------------------------------------------------+
 339 | vd/vs2 | vs1 | Meaning                                                                        |
 340 +========+=====+================================================================================+
 341 | 0      | 0   | srcbase is scalar, LD/ST is pure scalar.                                       |
 342 +--------+-----+--------------------------------------------------------------------------------+
 343 | 1      | 0   | srcbase is scalar, LD/ST is unit strided                                       |
 344 +--------+-----+--------------------------------------------------------------------------------+
 345 | 0      | 1   | srcbase is a vector (gather/scatter aka array of srcbases). VSPLAT and VSELECT |
 346 +--------+-----+--------------------------------------------------------------------------------+
 347 | 1      | 1   | srcbase is a vector, LD/ST is a full vector LD/ST.                             |
 348 +--------+-----+--------------------------------------------------------------------------------+
 349
 350 Notes:
 351
 352 * A register strided LD/ST would require *5* registers. srcbase, vd/vs2,
 353   predicate 1, predicate 2 and the stride register.
 354 * Complex strides may all be done with a general purpose vector of srcbases.
 355 * Twin predication may be used even when vd/vs1 is a scalar, to give
 356   VSPLAT and VSELECT, because the hardware loop ends on the first occurrence
 357   of a 1 in the predicate when a predicate is applied to a scalar.
 358 * Full vectorised gather/scatter is enabled when both registers are
 359   marked as vectorised, however unlike e.g Intel AVX512, twin predication
 360   can be applied.
 361
 362 Open question: RVV overloads the width field of LOAD-FP/STORE-FP
 363 using the bit 2 to indicate additional interpretation of the 11 bit
 364 immediate. Should this be considered?
 365
 366
 367 Sub-Vector Length (svlen) Field Encoding
 368 ========================================
 369
 370 NOTE: svlen is the same as the main spec SUBVL, and modifies the STATE
 371 CSR. The same caveats apply to svlen as do to SUBVL.
 372
 373 Bitwidth, from VL's perspective, is a multiple of the elwidth times svlen.
 374 So within each loop of VL there are svlen sub-elements of elwidth in size,
 375 just like in a SIMD architecture. When svlen is set to 0b00 (indicating
 376 svlen=1) no such SIMD-like behaviour exists and the subvectoring is
 377 disabled.
 378
 379 Predicate bits do not apply to the individual sub-vector elements, they
 380 apply to the entire subvector group. This saves instructions on setup
 381 of the predicate.
 382
 383 +----------------+-------+
 384 | svlen Encoding | Value |
 385 +================+=======+
 386 | 00             | SUBVL |
 387 +----------------+-------+
 388 | 01             | 2     |
 389 +----------------+-------+
 390 | 10             | 3     |
 391 +----------------+-------+
 392 | 11             | 4     |
 393 +----------------+-------+
 394
 395 In independent standalone implementations that do not implement the
 396 main specification, the value of SUBVL in the above table (svtyp=0b00)
 397 is set to 1, such that svlen is also 1.
 398
 399 Behaviour of operations that set svlen are identical to those of the
 400 main spec. See section on VLtyp, above.
 401
 402 Predication (pred) Field Encoding
 403 =================================
 404
 405 +------+------------+--------------------+----------------------------------------+
 406 | pred | Mnemonic   | Predicate Register | Meaning                                |
 407 +======+============+====================+========================================+
 408 | 000  | *None*     | *None*             | The instruction is unpredicated        |
 409 +------+------------+--------------------+----------------------------------------+
 410 | 001  | *Reserved* | *Reserved*         |                                        |
 411 +------+------------+--------------------+----------------------------------------+
 412 | 010  | !x9        | x9 (s1)            | execute vector op[0..i] on x9[i] == 0  |
 413 +------+------------+                    +----------------------------------------+
 414 | 011  | x9         |                    | execute vector op[0..i] on x9[i] == 1  |
 415 +------+------------+--------------------+----------------------------------------+
 416 | 100  | !x10       | x10 (a0)           | execute vector op[0..i] on x10[i] == 0 |
 417 +------+------------+                    +----------------------------------------+
 418 | 101  | x10        |                    | execute vector op[0..i] on x10[i] == 1 |
 419 +------+------------+--------------------+----------------------------------------+
 420 | 110  | !x11       | x11 (a1)           | execute vector op[0..i] on x11[i] == 0 |
 421 +------+------------+                    +----------------------------------------+
 422 | 111  | x11        |                    | execute vector op[0..i] on x11[i] == 1 |
 423 +------+------------+--------------------+----------------------------------------+
 424
 425 Twin-predication (tpred) Field Encoding
 426 =======================================
 427
 428 +-------+------------+--------------------+----------------------------------------------+
 429 | tpred | Mnemonic   | Predicate Register | Meaning                                      |
 430 +=======+============+====================+==============================================+
 431 | 000   | *None*     | *None*             | The instruction is unpredicated              |
 432 +-------+------------+--------------------+----------------------------------------------+
 433 | 001   | x9,off     | src=x9, dest=none  | src[0..i] uses x9[i], dest unpredicated      |
 434 +-------+------------+                    +----------------------------------------------+
 435 | 010   | off,x10    | src=none, dest=x10 | dest[0..i] uses x10[i], src unpredicated     |
 436 +-------+------------+                    +----------------------------------------------+
 437 | 011   | x9,10      | src=x9, dest=x10   | src[0..i] uses x9[i], dest[0..i] uses x10[i] |
 438 +-------+------------+--------------------+----------------------------------------------+
 439 | 100   | *None*     | *RESERVED*         | Instruction is unpredicated (TBD)            |
 440 +-------+------------+--------------------+----------------------------------------------+
 441 | 101   | !x9,off    | src=!x9, dest=none |                                              |
 442 +-------+------------+                    +----------------------------------------------+
 443 | 110   | off,!x10   | src=none, dest=!x10|                                              |
 444 +-------+------------+                    +----------------------------------------------+
 445 | 111   | !x9,!x10   | src=!x9, dest=!x10 |                                              |
 446 +-------+------------+--------------------+----------------------------------------------+
 447
 448 Integer Element Type (itype) Field Encoding
 449 ===========================================
 450
 451 +------------+-------+--------------+--------------+-----------------+-------------------+
 452 | Signedness | itype | Element Type | Mnemonic in  | Mnemonic in FP  | Meaning (INT may  |
 453 | [#sgn_def]_|       |              | Integer      | Instructions    | be un/signed, FP  |
 454 | [#sgn_def]_|       |              | Instructions | (such as fmv.x) | just re-sized     |
 455 +============+=======+==============+==============+=================+===================+
 456 | Unsigned   | 01    | u8           | BU           | BU              | Unsigned 8-bit    |
 457 |            +-------+--------------+--------------+-----------------+-------------------+
 458 |            | 10    | u16          | HU           | HU              | Unsigned 16-bit   |
 459 |            +-------+--------------+--------------+-----------------+-------------------+
 460 |            | 11    | u32          | WU           | WU              | Unsigned 32-bit   |
 461 |            +-------+--------------+--------------+-----------------+-------------------+
 462 |            | 00    | uXLEN        | WU/DU/QU     | WU/LU/TU        | Unsigned XLEN-bit |
 463 +------------+-------+--------------+--------------+-----------------+-------------------+
 464 | Signed     | 01    | i8           | BS           | BS              | Signed 8-bit      |
 465 |            +-------+--------------+--------------+-----------------+-------------------+
 466 |            | 10    | i16          | HS           | HS              | Signed 16-bit     |
 467 |            +-------+--------------+--------------+-----------------+-------------------+
 468 |            | 11    | i32          | W            | W               | Signed 32-bit     |
 469 |            +-------+--------------+--------------+-----------------+-------------------+
 470 |            | 00    | iXLEN        | W/D/Q        | W/L/T           | Signed XLEN-bit   |
 471 +------------+-------+--------------+--------------+-----------------+-------------------+
 472
 473 .. [#sgn_def] Signedness is defined in `Signedness Decision Procedure`_
 474
 475 Note: vector mode is effectively a type-cast of the register file
 476 as if it was a sequential array being typecast to typedef itype[]
 477 (c syntax).  The starting point of the "typecast" is the vector
 478 register rs#/rd.
 479
 480 Example: if itype=0b10 (u16), and rd is set to "vector", and
 481 VL is set to 4, the 64-bit register at rd is subdivided into
 482 *FOUR* 16-bit destination elements.  It is *NOT* four
 483 separate 64-bit destination registers (rd+0, rd+1, rd+2, rd+3)
 484 that are sign-extended from the source width size out to 64-bit,
 485 because that is itype=0b00 (uXLEN).
 486
 487 Note also: changing elwidth creates packed elements that, depending on
 488 VL, may create vectors that do not fit perfectly onto XLEN sized registry
 489 file bit-boundaries. This does NOT result in the destruction of the MSBs
 490 of the last register written to at the end of a VL loop. More details
 491 on how to handle this are described in the main Specification_.
 492
 493 Signedness Decision Procedure
 494 =============================
 495
 496 1. If the opcode field is either OP or OP-IMM, then
 497     1. Signedness is Unsigned.
 498 2. If the opcode field is either OP-32 or OP-IMM-32, then
 499     1. Signedness is Signed.
 500 3. If Signedness is encoded in a field of the base instruction, [#sign_enc]_ then
 501     1. Signedness uses the encoded value.
 502 4. Otherwise,
 503     1. Signedness is Unsigned.
 504
 505 .. [#sign_enc] Like in fcvt.d.l[u], but unlike in fmv.x.w,
 506                since there is no fmv.x.wu
 507
 508 Vector Type and Predication 5-bit (vtp5) Field Encoding
 509 =========================================================
 510
 511 In the following table, X denotes a wildcard that is 0 or 1 and can be
 512 a different value for every occurrence.
 513
 514 +-------+-----------+-----------+
 515 | vtp5  | pred      | svlen     |
 516 +=======+===========+===========+
 517 | 1XXXX | vtp5[4:2] | vtp5[1:0] |
 518 +-------+           |           |
 519 | 01XXX |           |           |
 520 +-------+           |           |
 521 | 000XX |           |           |
 522 +-------+-----------+-----------+
 523 | 001XX | *Reserved*            |
 524 +-------+-----------------------+
 525
 526 Vector Integer Type and Predication 6-bit (vitp6) Field Encoding
 527 =================================================================
 528
 529 In the following table, X denotes a wildcard that is 0 or 1 and can be a
 530 different value for every occurrence.
 531
 532 +--------+------------+---------+------------+------------+
 533 | vitp6  | itype      | pred[2] | pred[0:1]  | svlen      |
 534 +========+============+=========+============+============+
 535 | XX1XXX | vitp6[5:4] | 0       | vitp6[3:2] | vitp6[1:0] |
 536 +--------+            |         |            |            |
 537 | XX00XX |            |         |            |            |
 538 +--------+------------+---------+------------+------------+
 539 | XX01XX | *Reserved*                                     |
 540 +--------+------------------------------------------------+
 541
 542 vitp7 field: only tpred
 543
 544 +---------+------------+----------+-------------+------------+
 545 | vitp7   | itype      | tpred[2] | tpred[0:1]  | svlen      |
 546 +=========+============+==========+=============+============+
 547 | XXXXXXX | vitp7[5:4] | vitp7[6] | vitp7[3:2]  | vitp7[1:0] |
 548 +---------+------------+----------+-------------+------------+
 549
 550 48-bit Instruction Encoding Decision Procedure
 551 ==============================================
 552
 553 In the following decision procedure, *Reserved* means that there is not
 554 yet a defined 48-bit instruction encoding for the base instruction.
 555
 556 1. If the base instruction is a load instruction, then
 557     a. If the base instruction is an I-type instruction, then
 558         1. The encoding is P48-LD-type.
 559     b. Otherwise
 560         1. The encoding is *Reserved*.
 561 2. If the base instruction is a store instruction, then
 562     a. If the base instruction is an S-type instruction, then
 563         1. The encoding is P48-ST-type.
 564     b. Otherwise
 565         1. The encoding is *Reserved*.
 566 3. If the base instruction is a SYSTEM instruction, then
 567     a. The encoding is *Reserved*.
 568 4. If the base instruction is an integer instruction, then
 569     a. If the base instruction is an R-type instruction, then
 570         1. The encoding is P48-R-type.
 571     b. If the base instruction is an I-type instruction, then
 572         1. The encoding is P48-I-type.
 573     c. If the base instruction is an S-type instruction, then
 574         1. The encoding is *Reserved*.
 575     d. If the base instruction is an B-type instruction, then
 576         1. The encoding is *Reserved*.
 577     e. If the base instruction is an U-type instruction, then
 578         1. The encoding is P48-U-type.
 579     f. If the base instruction is an J-type instruction, then
 580         1. The encoding is *Reserved*.
 581     g. Otherwise
 582         1. The encoding is *Reserved*.
 583 5. If the base instruction is a floating-point instruction, then
 584     a. If the base instruction is an R-type instruction, then
 585         1. The encoding is P48-FR-type.
 586     b. If the base instruction is an I-type instruction, then
 587         1. The encoding is P48-FI-type.
 588     c. If the base instruction is an S-type instruction, then
 589         1. The encoding is *Reserved*.
 590     d. If the base instruction is an B-type instruction, then
 591         1. The encoding is *Reserved*.
 592     e. If the base instruction is an U-type instruction, then
 593         1. The encoding is *Reserved*.
 594     f. If the base instruction is an J-type instruction, then
 595         1. The encoding is *Reserved*.
 596     g. If the base instruction is an R4-type instruction, then
 597         1. The encoding is P48-FR4-type.
 598     h. Otherwise
 599         1. The encoding is *Reserved*.
 600 6. Otherwise
 601     a. The encoding is *Reserved*.
 602
 603 CSR Registers
 604 =============
 605
 606 CSRs are the same as in the main Specification_, if associated
 607 functionality is implemented. They have the exact same meaning as in
 608 the main specification.
 609
 610 * VL
 611 * MVL
 612 * STATE
 613 * SUBVL
 614
 615 Associated SET and GET on the CSRs is exactly as in the main spec as well
 616 (including CSRRWI and CSRRW differences).
 617
 618 Note that if all of VL/MVL, SUBVL, VLtyp and svlen are all chosen by an
 619 implementor not to be implemented, the STATE CSR is not required.
 620
 621 However if partial functionality is implemented, the unimplemented bits
 622 in STATE must be zero, and, in the UNIX Platform, an illegal exception
 623 **MUST** be raised if unsupported bits are written to.
 624
 625 Additional Instructions
 626 =======================
 627
 628 * Add instructions to convert between integer types.
 629 * Add instructions to `swizzle`_ elements in sub-vectors. Note that
 630   the sub-vector lengths of the source and destination won't necessarily
 631   match.
 632 * Add instructions to transpose (2-4)x(2-4) element matrices.
 633 * Add instructions to insert or extract a sub-vector from a vector, with
 634   the index allowed to be both immediate and from a register (*immediate
 635   can be covered by twin-predication, register might be, by virtue of
 636   predicates being registers*)
 637 * Add a register gather instruction (aka MV.X: regfile[rd] =
 638   regfile[regfile[rs1]])
 639
 640 subelement swizzle example:
 641
 642     velswizzle x32, x64, SRCSUBVL=3, DESTSUBVL=4, ELTYPE=u8, elements=[0, 0, 2, 1]
 643
 644 .. _swizzle: https://www.khronos.org/opengl/wiki/Data_Type_(GLSL)#Swizzling
 645
 646 questions
 647 =========
 648
 649 Moved to the discussion page (link at top of this page)
 650
 651 TODO
 652 ====
 653
 654 Work out a way to do sub-element swizzling.
 655