simple_v_extension/vblock_format_table.mdwn

   1 | base+4 ... base+2          | base             | number of bits             |
   2 | ------ -----------------   | ---------------- | -------------------------- |
   3 | ..xxxx  xxxxxxxxxxxxxxxx   | xnnnxxxxx1111111 | (80+16\*nnn)-bit, nnn!=111 |
   4 | {ops}{Pred}{Reg}{VL Block} | VBLOCK Prefix    |                            |
   5
   6 A suitable prefix, which fits the Expanded Instruction-Length encoding
   7 for "(80 + 16 times instruction-length)", as defined in Section 1.5
   8 of the RISC-V ISA, is as follows:
   9
  10 | 15    | 14:12 | 11:10 | 9:8   | 7    | 6:0     |
  11 | -     | ----- | ----- | ----- | ---  | ------- |
  12 | vlset | 16xil | pplen | rplen | mode | 1111111 |
  13
  14 The VL/MAXVL/SubVL Block format:
  15
  16 | 31-30 | 29:28 | 27:22  | 21:17  | 16  | comment |
  17 | -     | ----- | ------ | ------ | -   | -|
  18 | 0b00  | SubVL | VLdest | imm[4:0] | imm  | VL, bits 16-21 |
  19 | 0b01  | SubVL | MVLimm | VLreg    | VLd  | VLdest=t0,t1 |
  20 | 0b10  | SubVL | VLdest | imm[4:0] | imm | VL & MVL, bits 16-21 |
  21 | 0b11  | rsvd  | rsvd   | rsvd     | rsv | reserved, all 0s |
  22
  23
  24