simple_v_extension/vblock_format_table.mdwn

   1 | base+4 ... base+2          | base             | number of bits             |
   2 | ------ -----------------   | ---------------- | -------------------------- |
   3 | ..xxxx  xxxxxxxxxxxxxxxx   | xnnnxxxxx1111111 | (80+16\*nnn)-bit, nnn!=111 |
   4 | {ops}{Pred}{Reg}{VL Block} | VBLOCK Prefix    |                            |
   5
   6 A suitable prefix, which fits the Expanded Instruction-Length encoding
   7 for "(80 + 16 times instruction-length)", as defined in Section 1.5
   8 of the RISC-V ISA, is as follows:
   9
  10 | 15    | 14:12 | 11:10 | 9     | 8     | 7    | 6:0     |
  11 | -     | ----- | ----- | ----- | ----  | ---  | ------- |
  12 | vlset | 16xil | rplen | pplen | pmode | rmode | 1111111 |
  13
  14 The VL/MAXVL/SubVL Block format, when 16xil != 0b111, is:
  15
  16 [[!table  data="""
  17 31:30 | 29:28 | 27:22    | 21 | 20:19   | 18:16    | comment.................. |
  18 0b00  | SubVL | imm[5:0] |rsvd| rd[4:0]           || sv.setvl rd, x0, imm      |
  19 0b01  | SubVL | imm[5:0] | rs1[2:0]    || rd[2:0]  | sv.setvl rd, rs1, imm (1) |
  20 0b10  | SubVL | imm[5:0] |rsvd|  rs1[4:0]         || sv.setvl x0, rs1, imm     |
  21 0b11  | rsvd  | rsvd     |rsvd| rsvd              || reserved, all 0s          |
  22 """]]
  23
  24 Note (1) - Registers are in RVC format (x8-x15)
  25
  26 When 16xil is 0b111, this is the "Extended" Format, using the >= 192-bit
  27 RISC-V ISA format.  Note that the length is 96+16\*nnnnn, not 192+
  28
  29 | base+5 ... base+3         | base+1  | base             | no. of bits   |
  30 | ------ -----------------  |         | ---------------- | ------------- |
  31 | ..xxxx  xxxxxxxxxxxxxxxx  |         | x111xxxxx1111111 | 96+16\*nnnnn |
  32 | {ops}{Pred}{Reg}{VL Block}| VBLOCK2 | VBLOCK Prefix    |               |
  33
  34 VBLOCK2 extends the VBLOCK fields:
  35
  36 | 15:12 | 11:10  | 9:8    | 7:5   | 4:0  |
  37 | ----- | -----  | ----   | ---   | ---- |
  38 | rsvd  | rplen2 | pplen2 | swlen | ilen |
  39
  40 * ilen is the instruction length (number of 16-bit blocks)
  41 * swlen specifies the number of "swizzle" blocks
  42 * rplen2 extends rplen by 2 bits
  43 * pplen2 extends pplen by 2 bits
  44 * 4 bits are reserved for additional tables (Matrices?)