src/TLB/ariane/test/test_ptw.py

   1 import sys
   2 sys.path.append("../src")
   3 sys.path.append("../../../TestUtil")
   4
   5 from nmigen.compat.sim import run_simulation
   6
   7 from TLB.ariane.ptw import PTW, PTE
   8
   9 # unit was changed, test needs to be changed
  10
  11 def tbench(dut):
  12
  13     addr = 0x8000000
  14
  15     #pte = PTE()
  16     #yield pte.v.eq(1)
  17     #yield pte.r.eq(1)
  18
  19     yield dut.req_port_i.data_gnt.eq(1)
  20     yield dut.req_port_i.data_rvalid.eq(1)
  21     yield dut.req_port_i.data_rdata.eq(0x43)#pte.flatten())
  22
  23     # data lookup
  24     yield dut.en_ld_st_translation_i.eq(1)
  25     yield dut.asid_i.eq(1)
  26
  27     yield dut.dtlb_access_i.eq(1)
  28     yield dut.dtlb_hit_i.eq(0)
  29     yield dut.dtlb_vaddr_i.eq(0x400000000)
  30
  31     yield
  32     yield
  33     yield
  34
  35     yield dut.dtlb_access_i.eq(1)
  36     yield dut.dtlb_hit_i.eq(0)
  37     yield dut.dtlb_vaddr_i.eq(0x200000)
  38
  39     yield
  40     yield
  41     yield
  42
  43     yield dut.req_port_i.data_gnt.eq(0)
  44     yield dut.dtlb_access_i.eq(1)
  45     yield dut.dtlb_hit_i.eq(0)
  46     yield dut.dtlb_vaddr_i.eq(0x400000011)
  47
  48     yield
  49     yield dut.req_port_i.data_gnt.eq(1)
  50     yield
  51     yield
  52
  53     # data lookup, PTW levels 1-2-3
  54     addr = 0x4000000
  55     yield dut.dtlb_vaddr_i.eq(addr)
  56     yield dut.mxr_i.eq(0x1)
  57     yield dut.req_port_i.data_gnt.eq(1)
  58     yield dut.req_port_i.data_rvalid.eq(1)
  59     yield dut.req_port_i.data_rdata.eq(0x41 | (addr>>12)<<10)#pte.flatten())
  60
  61     yield dut.en_ld_st_translation_i.eq(1)
  62     yield dut.asid_i.eq(1)
  63
  64     yield dut.dtlb_access_i.eq(1)
  65     yield dut.dtlb_hit_i.eq(0)
  66     yield dut.dtlb_vaddr_i.eq(addr)
  67
  68     yield
  69     yield
  70     yield
  71     yield
  72     yield
  73     yield
  74     yield
  75     yield
  76
  77     yield dut.req_port_i.data_gnt.eq(0)
  78     yield dut.dtlb_access_i.eq(1)
  79     yield dut.dtlb_hit_i.eq(0)
  80     yield dut.dtlb_vaddr_i.eq(0x400000011)
  81
  82     yield
  83     yield dut.req_port_i.data_gnt.eq(1)
  84     yield
  85     yield
  86     yield
  87     yield
  88
  89
  90     # instruction lookup
  91     yield dut.en_ld_st_translation_i.eq(0)
  92     yield dut.enable_translation_i.eq(1)
  93     yield dut.asid_i.eq(1)
  94
  95     yield dut.itlb_access_i.eq(1)
  96     yield dut.itlb_hit_i.eq(0)
  97     yield dut.itlb_vaddr_i.eq(0x800000)
  98
  99     yield
 100     yield
 101     yield
 102
 103     yield dut.itlb_access_i.eq(1)
 104     yield dut.itlb_hit_i.eq(0)
 105     yield dut.itlb_vaddr_i.eq(0x200000)
 106
 107     yield
 108     yield
 109     yield
 110
 111     yield dut.req_port_i.data_gnt.eq(0)
 112     yield dut.itlb_access_i.eq(1)
 113     yield dut.itlb_hit_i.eq(0)
 114     yield dut.itlb_vaddr_i.eq(0x800011)
 115
 116     yield
 117     yield dut.req_port_i.data_gnt.eq(1)
 118     yield
 119     yield
 120
 121     yield
 122
 123
 124 def test_ptw():
 125     dut = PTW()
 126     run_simulation(dut, tbench(dut), vcd_name="test_ptw.vcd")
 127     print("PTW Unit Test Success")
 128
 129 if __name__ == "__main__":
 130     test_ptw()