src/TLB/test/test_cam.py

   1 from nmigen.compat.sim import run_simulation
   2
   3 from TLB.Cam import Cam
   4
   5 from TestUtil.test_helper import assert_eq, assert_ne, assert_op
   6
   7 # This function allows for the easy setting of values to the Cam
   8 # Arguments:
   9 #   dut: The Cam being tested
  10 #   e (Enable): Whether the block is going to be enabled
  11 #   we (Write Enable): Whether the Cam will write on the next cycle
  12 #   a (Address): Where the data will be written if write enable is high
  13 #   d (Data): Either what we are looking for or will write to the address
  14 def set_cam(dut, e, we, a, d):
  15     yield dut.enable.eq(e)
  16     yield dut.write_enable.eq(we)
  17     yield dut.address_in.eq(a)
  18     yield dut.data_in.eq(d)
  19     yield
  20
  21 # Checks the multiple match of the Cam
  22 # Arguments:
  23 #   dut: The Cam being tested
  24 #   mm (Multiple Match): The expected match result
  25 #   op (Operation): (0 => ==), (1 => !=)
  26 def check_multiple_match(dut, mm, op):
  27     out_mm = yield dut.multiple_match
  28     assert_op("Multiple Match", out_mm, mm, op)
  29
  30 # Checks the single match of the Cam
  31 # Arguments:
  32 #   dut: The Cam being tested
  33 #   sm (Single Match): The expected match result
  34 #   op (Operation): (0 => ==), (1 => !=)
  35 def check_single_match(dut, sm, op):
  36     out_sm = yield dut.single_match
  37     assert_op("Single Match", out_sm, sm, op)
  38
  39 # Checks the address output of the Cam
  40 # Arguments:
  41 #   dut: The Cam being tested
  42 #   ma (Match Address): The expected match result
  43 #   op (Operation): (0 => ==), (1 => !=)
  44 def check_match_address(dut, ma, op):
  45     out_ma = yield dut.match_address
  46     assert_op("Match Address", out_ma, ma, op)
  47
  48 # Checks the state of the Cam
  49 # Arguments:
  50 #   dut: The Cam being tested
  51 #   sm (Single Match): The expected match result
  52 #   mm (Multiple Match): The expected match result
  53 #   ma: (Match Address): The expected address output
  54 #   ss_op (Operation): Operation for the match assertion (0 => ==), (1 => !=)
  55 #   mm_op (Operation): Operation for the match assertion (0 => ==), (1 => !=)
  56 #   ma_op (Operation): Operation for the address assertion (0 => ==), (1 => !=)
  57 def check_all(dut, mm, sm, ma, mm_op, sm_op, ma_op):
  58     yield from check_multiple_match(dut, mm, mm_op)
  59     yield from check_single_match(dut, sm, sm_op)
  60     yield from check_match_address(dut, ma, ma_op)
  61
  62 def tbench(dut):
  63     # NA
  64     enable = 0
  65     write_enable = 0
  66     address = 0
  67     data = 0
  68     single_match = 0
  69     yield from set_cam(dut, enable, write_enable, address, data)
  70     yield
  71     yield from check_single_match(dut, single_match, 0)
  72
  73     # Read Miss Multiple
  74     # Note that the default starting entry data bits are all 0
  75     enable = 1
  76     write_enable = 0
  77     address = 0
  78     data = 0
  79     multiple_match = 1
  80     single_match = 0
  81     yield from set_cam(dut, enable, write_enable, address, data)
  82     yield
  83     yield from check_multiple_match(dut, multiple_match, 0)
  84
  85     # Read Miss
  86     # Note that the default starting entry data bits are all 0
  87     enable = 1
  88     write_enable = 0
  89     address = 0
  90     data = 1
  91     multiple_match = 0
  92     single_match = 0
  93     yield from set_cam(dut, enable, write_enable, address, data)
  94     yield
  95     yield from check_single_match(dut, single_match, 0)
  96
  97     # Write Entry 0
  98     enable = 1
  99     write_enable = 1
 100     address = 0
 101     data = 4
 102     multiple_match = 0
 103     single_match = 0
 104     yield from set_cam(dut, enable, write_enable, address, data)
 105     yield
 106     yield from check_single_match(dut, single_match, 0)
 107
 108     # Read Hit Entry 0
 109     enable = 1
 110     write_enable = 0
 111     address = 0
 112     data = 4
 113     multiple_match = 0
 114     single_match = 1
 115     yield from set_cam(dut, enable, write_enable, address, data)
 116     yield
 117     yield from check_all(dut, multiple_match, single_match, address, 0, 0, 0)
 118
 119     # Search Hit
 120     enable = 1
 121     write_enable = 0
 122     address = 0
 123     data = 4
 124     multiple_match = 0
 125     single_match = 1
 126     yield from set_cam(dut, enable, write_enable, address, data)
 127     yield
 128     yield from check_all(dut, multiple_match, single_match, address, 0, 0, 0)
 129
 130     # Search Miss
 131     enable = 1
 132     write_enable = 0
 133     address = 0
 134     data = 5
 135     single_match = 0
 136     yield from set_cam(dut, enable, write_enable, address, data)
 137     yield
 138     yield from check_single_match(dut, single_match, 0)
 139
 140     # Multiple Match test
 141     # Write Entry 1
 142     enable = 1
 143     write_enable = 1
 144     address = 1
 145     data = 5
 146     multiple_match = 0
 147     single_match = 0
 148     yield from set_cam(dut, enable, write_enable, address, data)
 149     yield
 150     yield from check_single_match(dut, single_match, 0)
 151
 152     # Write Entry 2
 153     # Same data as Entry 1
 154     enable = 1
 155     write_enable = 1
 156     address = 2
 157     data = 5
 158     multiple_match = 0
 159     single_match = 0
 160     yield from set_cam(dut, enable, write_enable, address, data)
 161     yield
 162     yield from check_single_match(dut, single_match, 0)
 163
 164     # Read Hit Data 5
 165     enable = 1
 166     write_enable = 0
 167     address = 1
 168     data = 5
 169     multiple_match = 1
 170     single_match = 0
 171     yield from set_cam(dut, enable, write_enable, address, data)
 172     yield
 173     yield from check_all(dut, multiple_match, single_match, address,0,0,0)
 174
 175     # Verify read_warning is not caused
 176     # Write Entry 0
 177     enable = 1
 178     write_enable = 1
 179     address = 0
 180     data = 7
 181     multiple_match = 0
 182     single_match = 0
 183     yield from set_cam(dut, enable, write_enable, address, data)
 184     # Note there is no yield we immediately attempt to read in the next cycle
 185
 186     # Read Hit Data 7
 187     enable = 1
 188     write_enable = 0
 189     address = 0
 190     data = 7
 191     multiple_match = 0
 192     single_match = 1
 193     yield from set_cam(dut, enable, write_enable, address, data)
 194     yield
 195     yield from check_single_match(dut, single_match, 0)
 196
 197     yield
 198
 199
 200 def test_cam():
 201     dut = Cam(4, 4)
 202     run_simulation(dut, tbench(dut), vcd_name="Waveforms/test_cam.vcd")
 203     print("Cam Unit Test Success")
 204
 205 if __name__ == "__main__":
 206     test_cam()