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start connecting FPNumBase2Ops
[ieee754fpu.git] / src / add / nmigen_add_experiment.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module, Signal, Cat, Mux, Array, Const
6 from nmigen.lib.coding import PriorityEncoder
7 from nmigen.cli import main, verilog
8 from math import log
9
10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
11 from fpbase import MultiShiftRMerge, Trigger
12 #from fpbase import FPNumShiftMultiRight
13
14
15 class FPState(FPBase):
16 def __init__(self, state_from):
17 self.state_from = state_from
18
19 def set_inputs(self, inputs):
20 self.inputs = inputs
21 for k,v in inputs.items():
22 setattr(self, k, v)
23
24 def set_outputs(self, outputs):
25 self.outputs = outputs
26 for k,v in outputs.items():
27 setattr(self, k, v)
28
29
30 class FPGetSyncOpsMod:
31 def __init__(self, width, num_ops=2):
32 self.width = width
33 self.num_ops = num_ops
34 inops = []
35 outops = []
36 for i in range(num_ops):
37 inops.append(Signal(width, reset_less=True))
38 outops.append(Signal(width, reset_less=True))
39 self.in_op = inops
40 self.out_op = outops
41 self.stb = Signal(num_ops)
42 self.ack = Signal()
43 self.ready = Signal(reset_less=True)
44 self.out_decode = Signal(reset_less=True)
45
46 def elaborate(self, platform):
47 m = Module()
48 m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
49 m.d.comb += self.out_decode.eq(self.ack & self.ready)
50 with m.If(self.out_decode):
51 for i in range(self.num_ops):
52 m.d.comb += [
53 self.out_op[i].eq(self.in_op[i]),
54 ]
55 return m
56
57 def ports(self):
58 return self.in_op + self.out_op + [self.stb, self.ack]
59
60
61 class FPOps(Trigger):
62 def __init__(self, width, num_ops):
63 Trigger.__init__(self)
64 self.width = width
65 self.num_ops = num_ops
66
67 res = []
68 for i in range(num_ops):
69 res.append(Signal(width))
70 self.v = Array(res)
71
72 def ports(self):
73 res = []
74 for i in range(self.num_ops):
75 res.append(self.v[i])
76 res.append(self.ack)
77 res.append(self.stb)
78 return res
79
80
81 class InputGroup:
82 def __init__(self, width, num_ops=2, num_rows=4):
83 self.width = width
84 self.num_ops = num_ops
85 self.num_rows = num_rows
86 self.mmax = int(log(self.num_rows) / log(2))
87 self.rs = []
88 self.mid = Signal(self.mmax, reset_less=True) # multiplex id
89 for i in range(num_rows):
90 self.rs.append(FPGetSyncOpsMod(width, num_ops))
91 self.rs = Array(self.rs)
92
93 self.out_op = FPOps(width, num_ops)
94
95 def elaborate(self, platform):
96 m = Module()
97
98 pe = PriorityEncoder(self.num_rows)
99 m.submodules.selector = pe
100 m.submodules.out_op = self.out_op
101 m.submodules += self.rs
102
103 # connect priority encoder
104 in_ready = []
105 for i in range(self.num_rows):
106 in_ready.append(self.rs[i].ready)
107 m.d.comb += pe.i.eq(Cat(*in_ready))
108
109 active = Signal(reset_less=True)
110 out_en = Signal(reset_less=True)
111 m.d.comb += active.eq(~pe.n) # encoder active
112 m.d.comb += out_en.eq(active & self.out_op.trigger)
113
114 # encoder active: ack relevant input, record MID, pass output
115 with m.If(out_en):
116 rs = self.rs[pe.o]
117 m.d.sync += self.mid.eq(pe.o)
118 m.d.sync += rs.ack.eq(0)
119 m.d.sync += self.out_op.stb.eq(0)
120 for j in range(self.num_ops):
121 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
122 with m.Else():
123 m.d.sync += self.out_op.stb.eq(1)
124 # acks all default to zero
125 for i in range(self.num_rows):
126 m.d.sync += self.rs[i].ack.eq(1)
127
128 return m
129
130 def ports(self):
131 res = []
132 for i in range(self.num_rows):
133 inop = self.rs[i]
134 res += inop.in_op + [inop.stb]
135 return self.out_op.ports() + res + [self.mid]
136
137
138 class FPGetOpMod:
139 def __init__(self, width):
140 self.in_op = FPOp(width)
141 self.out_op = Signal(width)
142 self.out_decode = Signal(reset_less=True)
143
144 def elaborate(self, platform):
145 m = Module()
146 m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
147 m.submodules.get_op_in = self.in_op
148 #m.submodules.get_op_out = self.out_op
149 with m.If(self.out_decode):
150 m.d.comb += [
151 self.out_op.eq(self.in_op.v),
152 ]
153 return m
154
155
156 class FPGetOp(FPState):
157 """ gets operand
158 """
159
160 def __init__(self, in_state, out_state, in_op, width):
161 FPState.__init__(self, in_state)
162 self.out_state = out_state
163 self.mod = FPGetOpMod(width)
164 self.in_op = in_op
165 self.out_op = Signal(width)
166 self.out_decode = Signal(reset_less=True)
167
168 def setup(self, m, in_op):
169 """ links module to inputs and outputs
170 """
171 setattr(m.submodules, self.state_from, self.mod)
172 m.d.comb += self.mod.in_op.eq(in_op)
173 #m.d.comb += self.out_op.eq(self.mod.out_op)
174 m.d.comb += self.out_decode.eq(self.mod.out_decode)
175
176 def action(self, m):
177 with m.If(self.out_decode):
178 m.next = self.out_state
179 m.d.sync += [
180 self.in_op.ack.eq(0),
181 self.out_op.eq(self.mod.out_op)
182 ]
183 with m.Else():
184 m.d.sync += self.in_op.ack.eq(1)
185
186
187 class FPGet2OpMod(Trigger):
188 def __init__(self, width, id_wid):
189 Trigger.__init__(self)
190 self.width = width
191 self.id_wid = id_wid
192 self.in_op1 = Signal(width, reset_less=True)
193 self.in_op2 = Signal(width, reset_less=True)
194 self.o = FPNumBase2Ops(width, id_wid)
195
196 def ospec(self):
197 return FPNumBase2Ops(self.width, self.id_wid)
198
199 def elaborate(self, platform):
200 m = Trigger.elaborate(self, platform)
201 #m.submodules.get_op_in = self.in_op
202 m.submodules.get_op1_out = self.o.a
203 m.submodules.get_op2_out = self.o.b
204 out_op1 = FPNumIn(None, self.width)
205 out_op2 = FPNumIn(None, self.width)
206 with m.If(self.trigger):
207 m.d.comb += [
208 out_op1.decode(self.in_op1),
209 out_op2.decode(self.in_op2),
210 self.o.a.eq(out_op1),
211 self.o.b.eq(out_op2),
212 ]
213 return m
214
215
216 class FPGet2Op(FPState):
217 """ gets operands
218 """
219
220 def __init__(self, in_state, out_state, in_op1, in_op2, width, id_wid):
221 FPState.__init__(self, in_state)
222 self.out_state = out_state
223 self.mod = FPGet2OpMod(width, id_wid)
224 self.in_op1 = in_op1
225 self.in_op2 = in_op2
226 self.o = self.mod.ospec()
227 self.in_stb = Signal(reset_less=True)
228 self.out_ack = Signal(reset_less=True)
229 self.out_decode = Signal(reset_less=True)
230
231 def setup(self, m, in_op1, in_op2, in_stb, in_ack):
232 """ links module to inputs and outputs
233 """
234 m.submodules.get_ops = self.mod
235 m.d.comb += self.mod.in_op1.eq(in_op1)
236 m.d.comb += self.mod.in_op2.eq(in_op2)
237 m.d.comb += self.mod.stb.eq(in_stb)
238 m.d.comb += self.out_ack.eq(self.mod.ack)
239 m.d.comb += self.out_decode.eq(self.mod.trigger)
240 m.d.comb += in_ack.eq(self.mod.ack)
241
242 def action(self, m):
243 with m.If(self.out_decode):
244 m.next = self.out_state
245 m.d.sync += [
246 self.mod.ack.eq(0),
247 #self.out_op1.v.eq(self.mod.out_op1.v),
248 #self.out_op2.v.eq(self.mod.out_op2.v),
249 self.o.eq(self.mod.o),
250 ]
251 with m.Else():
252 m.d.sync += self.mod.ack.eq(1)
253
254 class FPNumBase2Ops:
255
256 def __init__(self, width, id_wid, m_extra=True):
257 self.a = FPNumBase(width, m_extra)
258 self.b = FPNumBase(width, m_extra)
259 self.mid = Signal(id_wid, reset_less=True)
260
261 def eq(self, i):
262 return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
263
264
265 class FPAddSpecialCasesMod:
266 """ special cases: NaNs, infs, zeros, denormalised
267 NOTE: some of these are unique to add. see "Special Operations"
268 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
269 """
270
271 def __init__(self, width, id_wid):
272 self.width = width
273 self.id_wid = id_wid
274 self.i = self.ispec()
275 self.o = self.ospec()
276 self.out_do_z = Signal(reset_less=True)
277
278 def ispec(self):
279 return FPNumBase2Ops(self.width, self.id_wid)
280
281 def ospec(self):
282 return FPPackData(self.width, self.id_wid)
283
284 def setup(self, m, in_a, in_b, out_do_z):
285 """ links module to inputs and outputs
286 """
287 m.submodules.specialcases = self
288 m.d.comb += self.i.a.eq(in_a)
289 m.d.comb += self.i.b.eq(in_b)
290 m.d.comb += out_do_z.eq(self.out_do_z)
291
292 def elaborate(self, platform):
293 m = Module()
294
295 m.submodules.sc_in_a = self.i.a
296 m.submodules.sc_in_b = self.i.b
297 m.submodules.sc_out_z = self.o.z
298
299 s_nomatch = Signal()
300 m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
301
302 m_match = Signal()
303 m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
304
305 # if a is NaN or b is NaN return NaN
306 with m.If(self.i.a.is_nan | self.i.b.is_nan):
307 m.d.comb += self.out_do_z.eq(1)
308 m.d.comb += self.o.z.nan(0)
309
310 # XXX WEIRDNESS for FP16 non-canonical NaN handling
311 # under review
312
313 ## if a is zero and b is NaN return -b
314 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
315 # m.d.comb += self.out_do_z.eq(1)
316 # m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
317
318 ## if b is zero and a is NaN return -a
319 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
320 # m.d.comb += self.out_do_z.eq(1)
321 # m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
322
323 ## if a is -zero and b is NaN return -b
324 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
325 # m.d.comb += self.out_do_z.eq(1)
326 # m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
327
328 ## if b is -zero and a is NaN return -a
329 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
330 # m.d.comb += self.out_do_z.eq(1)
331 # m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
332
333 # if a is inf return inf (or NaN)
334 with m.Elif(self.i.a.is_inf):
335 m.d.comb += self.out_do_z.eq(1)
336 m.d.comb += self.o.z.inf(self.i.a.s)
337 # if a is inf and signs don't match return NaN
338 with m.If(self.i.b.exp_128 & s_nomatch):
339 m.d.comb += self.o.z.nan(0)
340
341 # if b is inf return inf
342 with m.Elif(self.i.b.is_inf):
343 m.d.comb += self.out_do_z.eq(1)
344 m.d.comb += self.o.z.inf(self.i.b.s)
345
346 # if a is zero and b zero return signed-a/b
347 with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
348 m.d.comb += self.out_do_z.eq(1)
349 m.d.comb += self.o.z.create(self.i.a.s & self.i.b.s,
350 self.i.b.e,
351 self.i.b.m[3:-1])
352
353 # if a is zero return b
354 with m.Elif(self.i.a.is_zero):
355 m.d.comb += self.out_do_z.eq(1)
356 m.d.comb += self.o.z.create(self.i.b.s, self.i.b.e,
357 self.i.b.m[3:-1])
358
359 # if b is zero return a
360 with m.Elif(self.i.b.is_zero):
361 m.d.comb += self.out_do_z.eq(1)
362 m.d.comb += self.o.z.create(self.i.a.s, self.i.a.e,
363 self.i.a.m[3:-1])
364
365 # if a equal to -b return zero (+ve zero)
366 with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
367 m.d.comb += self.out_do_z.eq(1)
368 m.d.comb += self.o.z.zero(0)
369
370 # Denormalised Number checks
371 with m.Else():
372 m.d.comb += self.out_do_z.eq(0)
373
374 return m
375
376
377 class FPID:
378 def __init__(self, id_wid):
379 self.id_wid = id_wid
380 if self.id_wid:
381 self.in_mid = Signal(id_wid, reset_less=True)
382 self.out_mid = Signal(id_wid, reset_less=True)
383 else:
384 self.in_mid = None
385 self.out_mid = None
386
387 def idsync(self, m):
388 if self.id_wid is not None:
389 m.d.sync += self.out_mid.eq(self.in_mid)
390
391
392 class FPAddSpecialCases(FPState, FPID):
393 """ special cases: NaNs, infs, zeros, denormalised
394 NOTE: some of these are unique to add. see "Special Operations"
395 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
396 """
397
398 def __init__(self, width, id_wid):
399 FPState.__init__(self, "special_cases")
400 FPID.__init__(self, id_wid)
401 self.mod = FPAddSpecialCasesMod(width)
402 self.out_z = self.mod.ospec()
403 self.out_do_z = Signal(reset_less=True)
404
405 def setup(self, m, in_a, in_b, in_mid):
406 """ links module to inputs and outputs
407 """
408 self.mod.setup(m, in_a, in_b, self.out_do_z)
409 if self.in_mid is not None:
410 m.d.comb += self.in_mid.eq(in_mid)
411
412 def action(self, m):
413 self.idsync(m)
414 with m.If(self.out_do_z):
415 m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
416 m.next = "put_z"
417 with m.Else():
418 m.next = "denormalise"
419
420
421 class FPAddSpecialCasesDeNorm(FPState, FPID):
422 """ special cases: NaNs, infs, zeros, denormalised
423 NOTE: some of these are unique to add. see "Special Operations"
424 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
425 """
426
427 def __init__(self, width, id_wid):
428 FPState.__init__(self, "special_cases")
429 FPID.__init__(self, id_wid)
430 self.smod = FPAddSpecialCasesMod(width, id_wid)
431 self.out_z = self.smod.ospec()
432 self.out_do_z = Signal(reset_less=True)
433
434 self.dmod = FPAddDeNormMod(width, id_wid)
435 self.o = self.dmod.ospec()
436
437 def setup(self, m, in_a, in_b, in_mid):
438 """ links module to inputs and outputs
439 """
440 self.smod.setup(m, in_a, in_b, self.out_do_z)
441 self.dmod.setup(m, in_a, in_b)
442 if self.in_mid is not None:
443 m.d.comb += self.in_mid.eq(in_mid)
444
445 def action(self, m):
446 self.idsync(m)
447 with m.If(self.out_do_z):
448 m.d.sync += self.out_z.z.v.eq(self.smod.o.z.v) # only take output
449 m.next = "put_z"
450 with m.Else():
451 m.next = "align"
452 m.d.sync += self.o.a.eq(self.dmod.o.a)
453 m.d.sync += self.o.b.eq(self.dmod.o.b)
454
455
456 class FPAddDeNormMod(FPState):
457
458 def __init__(self, width, id_wid):
459 self.width = width
460 self.id_wid = id_wid
461 self.i = self.ispec()
462 self.o = self.ospec()
463
464 def ispec(self):
465 return FPNumBase2Ops(self.width, self.id_wid)
466
467 def ospec(self):
468 return FPNumBase2Ops(self.width, self.id_wid)
469
470 def setup(self, m, in_a, in_b):
471 """ links module to inputs and outputs
472 """
473 m.submodules.denormalise = self
474 m.d.comb += self.i.a.eq(in_a)
475 m.d.comb += self.i.b.eq(in_b)
476
477 def elaborate(self, platform):
478 m = Module()
479 m.submodules.denorm_in_a = self.i.a
480 m.submodules.denorm_in_b = self.i.b
481 m.submodules.denorm_out_a = self.o.a
482 m.submodules.denorm_out_b = self.o.b
483 # hmmm, don't like repeating identical code
484 m.d.comb += self.o.a.eq(self.i.a)
485 with m.If(self.i.a.exp_n127):
486 m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
487 with m.Else():
488 m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
489
490 m.d.comb += self.o.b.eq(self.i.b)
491 with m.If(self.i.b.exp_n127):
492 m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
493 with m.Else():
494 m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
495
496 return m
497
498
499 class FPAddDeNorm(FPState, FPID):
500
501 def __init__(self, width, id_wid):
502 FPState.__init__(self, "denormalise")
503 FPID.__init__(self, id_wid)
504 self.mod = FPAddDeNormMod(width)
505 self.out_a = FPNumBase(width)
506 self.out_b = FPNumBase(width)
507
508 def setup(self, m, in_a, in_b, in_mid):
509 """ links module to inputs and outputs
510 """
511 self.mod.setup(m, in_a, in_b)
512 if self.in_mid is not None:
513 m.d.comb += self.in_mid.eq(in_mid)
514
515 def action(self, m):
516 self.idsync(m)
517 # Denormalised Number checks
518 m.next = "align"
519 m.d.sync += self.out_a.eq(self.mod.out_a)
520 m.d.sync += self.out_b.eq(self.mod.out_b)
521
522
523 class FPAddAlignMultiMod(FPState):
524
525 def __init__(self, width):
526 self.in_a = FPNumBase(width)
527 self.in_b = FPNumBase(width)
528 self.out_a = FPNumIn(None, width)
529 self.out_b = FPNumIn(None, width)
530 self.exp_eq = Signal(reset_less=True)
531
532 def elaborate(self, platform):
533 # This one however (single-cycle) will do the shift
534 # in one go.
535
536 m = Module()
537
538 m.submodules.align_in_a = self.in_a
539 m.submodules.align_in_b = self.in_b
540 m.submodules.align_out_a = self.out_a
541 m.submodules.align_out_b = self.out_b
542
543 # NOTE: this does *not* do single-cycle multi-shifting,
544 # it *STAYS* in the align state until exponents match
545
546 # exponent of a greater than b: shift b down
547 m.d.comb += self.exp_eq.eq(0)
548 m.d.comb += self.out_a.eq(self.in_a)
549 m.d.comb += self.out_b.eq(self.in_b)
550 agtb = Signal(reset_less=True)
551 altb = Signal(reset_less=True)
552 m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
553 m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
554 with m.If(agtb):
555 m.d.comb += self.out_b.shift_down(self.in_b)
556 # exponent of b greater than a: shift a down
557 with m.Elif(altb):
558 m.d.comb += self.out_a.shift_down(self.in_a)
559 # exponents equal: move to next stage.
560 with m.Else():
561 m.d.comb += self.exp_eq.eq(1)
562 return m
563
564
565 class FPAddAlignMulti(FPState, FPID):
566
567 def __init__(self, width, id_wid):
568 FPID.__init__(self, id_wid)
569 FPState.__init__(self, "align")
570 self.mod = FPAddAlignMultiMod(width)
571 self.out_a = FPNumIn(None, width)
572 self.out_b = FPNumIn(None, width)
573 self.exp_eq = Signal(reset_less=True)
574
575 def setup(self, m, in_a, in_b, in_mid):
576 """ links module to inputs and outputs
577 """
578 m.submodules.align = self.mod
579 m.d.comb += self.mod.in_a.eq(in_a)
580 m.d.comb += self.mod.in_b.eq(in_b)
581 #m.d.comb += self.out_a.eq(self.mod.out_a)
582 #m.d.comb += self.out_b.eq(self.mod.out_b)
583 m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
584 if self.in_mid is not None:
585 m.d.comb += self.in_mid.eq(in_mid)
586
587 def action(self, m):
588 self.idsync(m)
589 m.d.sync += self.out_a.eq(self.mod.out_a)
590 m.d.sync += self.out_b.eq(self.mod.out_b)
591 with m.If(self.exp_eq):
592 m.next = "add_0"
593
594
595 class FPNumIn2Ops:
596
597 def __init__(self, width, id_wid):
598 self.a = FPNumIn(None, width)
599 self.b = FPNumIn(None, width)
600 self.mid = Signal(id_wid, reset_less=True)
601
602 def eq(self, i):
603 return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
604
605
606 class FPAddAlignSingleMod:
607
608 def __init__(self, width, id_wid):
609 self.width = width
610 self.id_wid = id_wid
611 self.i = self.ispec()
612 self.o = self.ospec()
613
614 def ispec(self):
615 return FPNumBase2Ops(self.width, self.id_wid)
616
617 def ospec(self):
618 return FPNumIn2Ops(self.width, self.id_wid)
619
620 def setup(self, m, in_a, in_b):
621 """ links module to inputs and outputs
622 """
623 m.submodules.align = self
624 m.d.comb += self.i.a.eq(in_a)
625 m.d.comb += self.i.b.eq(in_b)
626
627 def elaborate(self, platform):
628 """ Aligns A against B or B against A, depending on which has the
629 greater exponent. This is done in a *single* cycle using
630 variable-width bit-shift
631
632 the shifter used here is quite expensive in terms of gates.
633 Mux A or B in (and out) into temporaries, as only one of them
634 needs to be aligned against the other
635 """
636 m = Module()
637
638 m.submodules.align_in_a = self.i.a
639 m.submodules.align_in_b = self.i.b
640 m.submodules.align_out_a = self.o.a
641 m.submodules.align_out_b = self.o.b
642
643 # temporary (muxed) input and output to be shifted
644 t_inp = FPNumBase(self.width)
645 t_out = FPNumIn(None, self.width)
646 espec = (len(self.i.a.e), True)
647 msr = MultiShiftRMerge(self.i.a.m_width, espec)
648 m.submodules.align_t_in = t_inp
649 m.submodules.align_t_out = t_out
650 m.submodules.multishift_r = msr
651
652 ediff = Signal(espec, reset_less=True)
653 ediffr = Signal(espec, reset_less=True)
654 tdiff = Signal(espec, reset_less=True)
655 elz = Signal(reset_less=True)
656 egz = Signal(reset_less=True)
657
658 # connect multi-shifter to t_inp/out mantissa (and tdiff)
659 m.d.comb += msr.inp.eq(t_inp.m)
660 m.d.comb += msr.diff.eq(tdiff)
661 m.d.comb += t_out.m.eq(msr.m)
662 m.d.comb += t_out.e.eq(t_inp.e + tdiff)
663 m.d.comb += t_out.s.eq(t_inp.s)
664
665 m.d.comb += ediff.eq(self.i.a.e - self.i.b.e)
666 m.d.comb += ediffr.eq(self.i.b.e - self.i.a.e)
667 m.d.comb += elz.eq(self.i.a.e < self.i.b.e)
668 m.d.comb += egz.eq(self.i.a.e > self.i.b.e)
669
670 # default: A-exp == B-exp, A and B untouched (fall through)
671 m.d.comb += self.o.a.eq(self.i.a)
672 m.d.comb += self.o.b.eq(self.i.b)
673 # only one shifter (muxed)
674 #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
675 # exponent of a greater than b: shift b down
676 with m.If(egz):
677 m.d.comb += [t_inp.eq(self.i.b),
678 tdiff.eq(ediff),
679 self.o.b.eq(t_out),
680 self.o.b.s.eq(self.i.b.s), # whoops forgot sign
681 ]
682 # exponent of b greater than a: shift a down
683 with m.Elif(elz):
684 m.d.comb += [t_inp.eq(self.i.a),
685 tdiff.eq(ediffr),
686 self.o.a.eq(t_out),
687 self.o.a.s.eq(self.i.a.s), # whoops forgot sign
688 ]
689 return m
690
691
692 class FPAddAlignSingle(FPState, FPID):
693
694 def __init__(self, width, id_wid):
695 FPState.__init__(self, "align")
696 FPID.__init__(self, id_wid)
697 self.mod = FPAddAlignSingleMod(width, id_wid)
698 self.out_a = FPNumIn(None, width)
699 self.out_b = FPNumIn(None, width)
700
701 def setup(self, m, in_a, in_b, in_mid):
702 """ links module to inputs and outputs
703 """
704 self.mod.setup(m, in_a, in_b)
705 if self.in_mid is not None:
706 m.d.comb += self.in_mid.eq(in_mid)
707
708 def action(self, m):
709 self.idsync(m)
710 # NOTE: could be done as comb
711 m.d.sync += self.out_a.eq(self.mod.out_a)
712 m.d.sync += self.out_b.eq(self.mod.out_b)
713 m.next = "add_0"
714
715
716 class FPAddAlignSingleAdd(FPState, FPID):
717
718 def __init__(self, width, id_wid):
719 FPState.__init__(self, "align")
720 FPID.__init__(self, id_wid)
721 self.mod = FPAddAlignSingleMod(width, id_wid)
722 self.o = self.mod.ospec()
723
724 self.a0mod = FPAddStage0Mod(width, id_wid)
725 self.a0o = self.a0mod.ospec()
726
727 self.a1mod = FPAddStage1Mod(width, id_wid)
728 self.a1o = self.a1mod.ospec()
729
730 def setup(self, m, in_a, in_b, in_mid):
731 """ links module to inputs and outputs
732 """
733 self.mod.setup(m, in_a, in_b)
734 m.d.comb += self.o.eq(self.mod.o)
735
736 self.a0mod.setup(m, self.o.a, self.o.b)
737 m.d.comb += self.a0o.eq(self.a0mod.o)
738
739 self.a1mod.setup(m, self.a0o.tot, self.a0o.z)
740
741 if self.in_mid is not None:
742 m.d.comb += self.in_mid.eq(in_mid)
743
744 def action(self, m):
745 self.idsync(m)
746 m.d.sync += self.a1o.eq(self.a1mod.o)
747 m.next = "normalise_1"
748
749
750 class FPAddStage0Data:
751
752 def __init__(self, width, id_wid):
753 self.z = FPNumBase(width, False)
754 self.tot = Signal(self.z.m_width + 4, reset_less=True)
755 self.mid = Signal(id_wid, reset_less=True)
756
757 def eq(self, i):
758 return [self.z.eq(i.z), self.tot.eq(i.tot), self.mid.eq(i.mid)]
759
760
761 class FPAddStage0Mod:
762
763 def __init__(self, width, id_wid):
764 self.width = width
765 self.id_wid = id_wid
766 self.i = self.ispec()
767 self.o = self.ospec()
768
769 def ispec(self):
770 return FPNumBase2Ops(self.width, self.id_wid)
771
772 def ospec(self):
773 return FPAddStage0Data(self.width, self.id_wid)
774
775 def setup(self, m, in_a, in_b):
776 """ links module to inputs and outputs
777 """
778 m.submodules.add0 = self
779 m.d.comb += self.i.a.eq(in_a)
780 m.d.comb += self.i.b.eq(in_b)
781
782 def elaborate(self, platform):
783 m = Module()
784 m.submodules.add0_in_a = self.i.a
785 m.submodules.add0_in_b = self.i.b
786 m.submodules.add0_out_z = self.o.z
787
788 m.d.comb += self.o.z.e.eq(self.i.a.e)
789
790 # store intermediate tests (and zero-extended mantissas)
791 seq = Signal(reset_less=True)
792 mge = Signal(reset_less=True)
793 am0 = Signal(len(self.i.a.m)+1, reset_less=True)
794 bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
795 m.d.comb += [seq.eq(self.i.a.s == self.i.b.s),
796 mge.eq(self.i.a.m >= self.i.b.m),
797 am0.eq(Cat(self.i.a.m, 0)),
798 bm0.eq(Cat(self.i.b.m, 0))
799 ]
800 # same-sign (both negative or both positive) add mantissas
801 with m.If(seq):
802 m.d.comb += [
803 self.o.tot.eq(am0 + bm0),
804 self.o.z.s.eq(self.i.a.s)
805 ]
806 # a mantissa greater than b, use a
807 with m.Elif(mge):
808 m.d.comb += [
809 self.o.tot.eq(am0 - bm0),
810 self.o.z.s.eq(self.i.a.s)
811 ]
812 # b mantissa greater than a, use b
813 with m.Else():
814 m.d.comb += [
815 self.o.tot.eq(bm0 - am0),
816 self.o.z.s.eq(self.i.b.s)
817 ]
818 return m
819
820
821 class FPAddStage0(FPState, FPID):
822 """ First stage of add. covers same-sign (add) and subtract
823 special-casing when mantissas are greater or equal, to
824 give greatest accuracy.
825 """
826
827 def __init__(self, width, id_wid):
828 FPState.__init__(self, "add_0")
829 FPID.__init__(self, id_wid)
830 self.mod = FPAddStage0Mod(width)
831 self.o = self.mod.ospec()
832
833 def setup(self, m, in_a, in_b, in_mid):
834 """ links module to inputs and outputs
835 """
836 self.mod.setup(m, in_a, in_b)
837 if self.in_mid is not None:
838 m.d.comb += self.in_mid.eq(in_mid)
839
840 def action(self, m):
841 self.idsync(m)
842 # NOTE: these could be done as combinatorial (merge add0+add1)
843 m.d.sync += self.o.eq(self.mod.o)
844 m.next = "add_1"
845
846
847 class FPAddStage1Data:
848
849 def __init__(self, width, id_wid):
850 self.z = FPNumBase(width, False)
851 self.of = Overflow()
852 self.mid = Signal(id_wid, reset_less=True)
853
854 def eq(self, i):
855 return [self.z.eq(i.z), self.of.eq(i.of), self.mid.eq(i.mid)]
856
857
858
859 class FPAddStage1Mod(FPState):
860 """ Second stage of add: preparation for normalisation.
861 detects when tot sum is too big (tot[27] is kinda a carry bit)
862 """
863
864 def __init__(self, width, id_wid):
865 self.width = width
866 self.id_wid = id_wid
867 self.i = self.ispec()
868 self.o = self.ospec()
869
870 def ispec(self):
871 return FPAddStage0Data(self.width, self.id_wid)
872
873 def ospec(self):
874 return FPAddStage1Data(self.width, self.id_wid)
875
876 def setup(self, m, in_tot, in_z):
877 """ links module to inputs and outputs
878 """
879 m.submodules.add1 = self
880 m.submodules.add1_out_overflow = self.o.of
881
882 m.d.comb += self.i.z.eq(in_z)
883 m.d.comb += self.i.tot.eq(in_tot)
884
885 def elaborate(self, platform):
886 m = Module()
887 #m.submodules.norm1_in_overflow = self.in_of
888 #m.submodules.norm1_out_overflow = self.out_of
889 #m.submodules.norm1_in_z = self.in_z
890 #m.submodules.norm1_out_z = self.out_z
891 m.d.comb += self.o.z.eq(self.i.z)
892 # tot[-1] (MSB) gets set when the sum overflows. shift result down
893 with m.If(self.i.tot[-1]):
894 m.d.comb += [
895 self.o.z.m.eq(self.i.tot[4:]),
896 self.o.of.m0.eq(self.i.tot[4]),
897 self.o.of.guard.eq(self.i.tot[3]),
898 self.o.of.round_bit.eq(self.i.tot[2]),
899 self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
900 self.o.z.e.eq(self.i.z.e + 1)
901 ]
902 # tot[-1] (MSB) zero case
903 with m.Else():
904 m.d.comb += [
905 self.o.z.m.eq(self.i.tot[3:]),
906 self.o.of.m0.eq(self.i.tot[3]),
907 self.o.of.guard.eq(self.i.tot[2]),
908 self.o.of.round_bit.eq(self.i.tot[1]),
909 self.o.of.sticky.eq(self.i.tot[0])
910 ]
911 return m
912
913
914 class FPAddStage1(FPState, FPID):
915
916 def __init__(self, width, id_wid):
917 FPState.__init__(self, "add_1")
918 FPID.__init__(self, id_wid)
919 self.mod = FPAddStage1Mod(width)
920 self.out_z = FPNumBase(width, False)
921 self.out_of = Overflow()
922 self.norm_stb = Signal()
923
924 def setup(self, m, in_tot, in_z, in_mid):
925 """ links module to inputs and outputs
926 """
927 self.mod.setup(m, in_tot, in_z)
928
929 m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
930
931 if self.in_mid is not None:
932 m.d.comb += self.in_mid.eq(in_mid)
933
934 def action(self, m):
935 self.idsync(m)
936 m.d.sync += self.out_of.eq(self.mod.out_of)
937 m.d.sync += self.out_z.eq(self.mod.out_z)
938 m.d.sync += self.norm_stb.eq(1)
939 m.next = "normalise_1"
940
941
942 class FPNormaliseModSingle:
943
944 def __init__(self, width):
945 self.width = width
946 self.in_z = self.ispec()
947 self.out_z = self.ospec()
948
949 def ispec(self):
950 return FPNumBase(self.width, False)
951
952 def ospec(self):
953 return FPNumBase(self.width, False)
954
955 def setup(self, m, in_z, out_z):
956 """ links module to inputs and outputs
957 """
958 m.submodules.normalise = self
959 m.d.comb += self.in_z.eq(in_z)
960 m.d.comb += out_z.eq(self.out_z)
961
962 def elaborate(self, platform):
963 m = Module()
964
965 mwid = self.out_z.m_width+2
966 pe = PriorityEncoder(mwid)
967 m.submodules.norm_pe = pe
968
969 m.submodules.norm1_out_z = self.out_z
970 m.submodules.norm1_in_z = self.in_z
971
972 in_z = FPNumBase(self.width, False)
973 in_of = Overflow()
974 m.submodules.norm1_insel_z = in_z
975 m.submodules.norm1_insel_overflow = in_of
976
977 espec = (len(in_z.e), True)
978 ediff_n126 = Signal(espec, reset_less=True)
979 msr = MultiShiftRMerge(mwid, espec)
980 m.submodules.multishift_r = msr
981
982 m.d.comb += in_z.eq(self.in_z)
983 m.d.comb += in_of.eq(self.in_of)
984 # initialise out from in (overridden below)
985 m.d.comb += self.out_z.eq(in_z)
986 m.d.comb += self.out_of.eq(in_of)
987 # normalisation decrease condition
988 decrease = Signal(reset_less=True)
989 m.d.comb += decrease.eq(in_z.m_msbzero)
990 # decrease exponent
991 with m.If(decrease):
992 # *sigh* not entirely obvious: count leading zeros (clz)
993 # with a PriorityEncoder: to find from the MSB
994 # we reverse the order of the bits.
995 temp_m = Signal(mwid, reset_less=True)
996 temp_s = Signal(mwid+1, reset_less=True)
997 clz = Signal((len(in_z.e), True), reset_less=True)
998 m.d.comb += [
999 # cat round and guard bits back into the mantissa
1000 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
1001 pe.i.eq(temp_m[::-1]), # inverted
1002 clz.eq(pe.o), # count zeros from MSB down
1003 temp_s.eq(temp_m << clz), # shift mantissa UP
1004 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
1005 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
1006 ]
1007
1008 return m
1009
1010 class FPNorm1Data:
1011
1012 def __init__(self, width, id_wid):
1013 self.roundz = Signal(reset_less=True)
1014 self.z = FPNumBase(width, False)
1015 self.mid = Signal(id_wid, reset_less=True)
1016
1017 def eq(self, i):
1018 return [self.z.eq(i.z), self.roundz.eq(i.roundz), self.mid.eq(i.mid)]
1019
1020
1021 class FPNorm1ModSingle:
1022
1023 def __init__(self, width, id_wid):
1024 self.width = width
1025 self.id_wid = id_wid
1026 self.i = self.ispec()
1027 self.o = self.ospec()
1028
1029 def ispec(self):
1030 return FPAddStage1Data(self.width, self.id_wid)
1031
1032 def ospec(self):
1033 return FPNorm1Data(self.width, self.id_wid)
1034
1035 def setup(self, m, in_z, in_of, out_z):
1036 """ links module to inputs and outputs
1037 """
1038 m.submodules.normalise_1 = self
1039
1040 m.d.comb += self.i.z.eq(in_z)
1041 m.d.comb += self.i.of.eq(in_of)
1042
1043 m.d.comb += out_z.eq(self.o.z)
1044
1045 def elaborate(self, platform):
1046 m = Module()
1047
1048 mwid = self.o.z.m_width+2
1049 pe = PriorityEncoder(mwid)
1050 m.submodules.norm_pe = pe
1051
1052 of = Overflow()
1053 m.d.comb += self.o.roundz.eq(of.roundz)
1054
1055 m.submodules.norm1_out_z = self.o.z
1056 m.submodules.norm1_out_overflow = of
1057 m.submodules.norm1_in_z = self.i.z
1058 m.submodules.norm1_in_overflow = self.i.of
1059
1060 i = self.ispec()
1061 m.submodules.norm1_insel_z = i.z
1062 m.submodules.norm1_insel_overflow = i.of
1063
1064 espec = (len(i.z.e), True)
1065 ediff_n126 = Signal(espec, reset_less=True)
1066 msr = MultiShiftRMerge(mwid, espec)
1067 m.submodules.multishift_r = msr
1068
1069 m.d.comb += i.eq(self.i)
1070 # initialise out from in (overridden below)
1071 m.d.comb += self.o.z.eq(i.z)
1072 m.d.comb += of.eq(i.of)
1073 # normalisation increase/decrease conditions
1074 decrease = Signal(reset_less=True)
1075 increase = Signal(reset_less=True)
1076 m.d.comb += decrease.eq(i.z.m_msbzero & i.z.exp_gt_n126)
1077 m.d.comb += increase.eq(i.z.exp_lt_n126)
1078 # decrease exponent
1079 with m.If(decrease):
1080 # *sigh* not entirely obvious: count leading zeros (clz)
1081 # with a PriorityEncoder: to find from the MSB
1082 # we reverse the order of the bits.
1083 temp_m = Signal(mwid, reset_less=True)
1084 temp_s = Signal(mwid+1, reset_less=True)
1085 clz = Signal((len(i.z.e), True), reset_less=True)
1086 # make sure that the amount to decrease by does NOT
1087 # go below the minimum non-INF/NaN exponent
1088 limclz = Mux(i.z.exp_sub_n126 > pe.o, pe.o,
1089 i.z.exp_sub_n126)
1090 m.d.comb += [
1091 # cat round and guard bits back into the mantissa
1092 temp_m.eq(Cat(i.of.round_bit, i.of.guard, i.z.m)),
1093 pe.i.eq(temp_m[::-1]), # inverted
1094 clz.eq(limclz), # count zeros from MSB down
1095 temp_s.eq(temp_m << clz), # shift mantissa UP
1096 self.o.z.e.eq(i.z.e - clz), # DECREASE exponent
1097 self.o.z.m.eq(temp_s[2:]), # exclude bits 0&1
1098 of.m0.eq(temp_s[2]), # copy of mantissa[0]
1099 # overflow in bits 0..1: got shifted too (leave sticky)
1100 of.guard.eq(temp_s[1]), # guard
1101 of.round_bit.eq(temp_s[0]), # round
1102 ]
1103 # increase exponent
1104 with m.Elif(increase):
1105 temp_m = Signal(mwid+1, reset_less=True)
1106 m.d.comb += [
1107 temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
1108 i.z.m)),
1109 ediff_n126.eq(i.z.N126 - i.z.e),
1110 # connect multi-shifter to inp/out mantissa (and ediff)
1111 msr.inp.eq(temp_m),
1112 msr.diff.eq(ediff_n126),
1113 self.o.z.m.eq(msr.m[3:]),
1114 of.m0.eq(temp_s[3]), # copy of mantissa[0]
1115 # overflow in bits 0..1: got shifted too (leave sticky)
1116 of.guard.eq(temp_s[2]), # guard
1117 of.round_bit.eq(temp_s[1]), # round
1118 of.sticky.eq(temp_s[0]), # sticky
1119 self.o.z.e.eq(i.z.e + ediff_n126),
1120 ]
1121
1122 return m
1123
1124
1125 class FPNorm1ModMulti:
1126
1127 def __init__(self, width, single_cycle=True):
1128 self.width = width
1129 self.in_select = Signal(reset_less=True)
1130 self.in_z = FPNumBase(width, False)
1131 self.in_of = Overflow()
1132 self.temp_z = FPNumBase(width, False)
1133 self.temp_of = Overflow()
1134 self.out_z = FPNumBase(width, False)
1135 self.out_of = Overflow()
1136
1137 def elaborate(self, platform):
1138 m = Module()
1139
1140 m.submodules.norm1_out_z = self.out_z
1141 m.submodules.norm1_out_overflow = self.out_of
1142 m.submodules.norm1_temp_z = self.temp_z
1143 m.submodules.norm1_temp_of = self.temp_of
1144 m.submodules.norm1_in_z = self.in_z
1145 m.submodules.norm1_in_overflow = self.in_of
1146
1147 in_z = FPNumBase(self.width, False)
1148 in_of = Overflow()
1149 m.submodules.norm1_insel_z = in_z
1150 m.submodules.norm1_insel_overflow = in_of
1151
1152 # select which of temp or in z/of to use
1153 with m.If(self.in_select):
1154 m.d.comb += in_z.eq(self.in_z)
1155 m.d.comb += in_of.eq(self.in_of)
1156 with m.Else():
1157 m.d.comb += in_z.eq(self.temp_z)
1158 m.d.comb += in_of.eq(self.temp_of)
1159 # initialise out from in (overridden below)
1160 m.d.comb += self.out_z.eq(in_z)
1161 m.d.comb += self.out_of.eq(in_of)
1162 # normalisation increase/decrease conditions
1163 decrease = Signal(reset_less=True)
1164 increase = Signal(reset_less=True)
1165 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1166 m.d.comb += increase.eq(in_z.exp_lt_n126)
1167 m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1168 # decrease exponent
1169 with m.If(decrease):
1170 m.d.comb += [
1171 self.out_z.e.eq(in_z.e - 1), # DECREASE exponent
1172 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1173 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1174 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1175 self.out_of.round_bit.eq(0), # reset round bit
1176 self.out_of.m0.eq(in_of.guard),
1177 ]
1178 # increase exponent
1179 with m.Elif(increase):
1180 m.d.comb += [
1181 self.out_z.e.eq(in_z.e + 1), # INCREASE exponent
1182 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1183 self.out_of.guard.eq(in_z.m[0]),
1184 self.out_of.m0.eq(in_z.m[1]),
1185 self.out_of.round_bit.eq(in_of.guard),
1186 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1187 ]
1188
1189 return m
1190
1191
1192 class FPNorm1Single(FPState, FPID):
1193
1194 def __init__(self, width, id_wid, single_cycle=True):
1195 FPID.__init__(self, id_wid)
1196 FPState.__init__(self, "normalise_1")
1197 self.mod = FPNorm1ModSingle(width)
1198 self.out_z = FPNumBase(width, False)
1199 self.out_roundz = Signal(reset_less=True)
1200
1201 def setup(self, m, in_z, in_of, in_mid):
1202 """ links module to inputs and outputs
1203 """
1204 self.mod.setup(m, in_z, in_of, self.out_z)
1205
1206 if self.in_mid is not None:
1207 m.d.comb += self.in_mid.eq(in_mid)
1208
1209 def action(self, m):
1210 self.idsync(m)
1211 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1212 m.next = "round"
1213
1214
1215 class FPNorm1Multi(FPState, FPID):
1216
1217 def __init__(self, width, id_wid):
1218 FPID.__init__(self, id_wid)
1219 FPState.__init__(self, "normalise_1")
1220 self.mod = FPNorm1ModMulti(width)
1221 self.stb = Signal(reset_less=True)
1222 self.ack = Signal(reset=0, reset_less=True)
1223 self.out_norm = Signal(reset_less=True)
1224 self.in_accept = Signal(reset_less=True)
1225 self.temp_z = FPNumBase(width)
1226 self.temp_of = Overflow()
1227 self.out_z = FPNumBase(width)
1228 self.out_roundz = Signal(reset_less=True)
1229
1230 def setup(self, m, in_z, in_of, norm_stb, in_mid):
1231 """ links module to inputs and outputs
1232 """
1233 self.mod.setup(m, in_z, in_of, norm_stb,
1234 self.in_accept, self.temp_z, self.temp_of,
1235 self.out_z, self.out_norm)
1236
1237 m.d.comb += self.stb.eq(norm_stb)
1238 m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1239
1240 if self.in_mid is not None:
1241 m.d.comb += self.in_mid.eq(in_mid)
1242
1243 def action(self, m):
1244 self.idsync(m)
1245 m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1246 m.d.sync += self.temp_of.eq(self.mod.out_of)
1247 m.d.sync += self.temp_z.eq(self.out_z)
1248 with m.If(self.out_norm):
1249 with m.If(self.in_accept):
1250 m.d.sync += [
1251 self.ack.eq(1),
1252 ]
1253 with m.Else():
1254 m.d.sync += self.ack.eq(0)
1255 with m.Else():
1256 # normalisation not required (or done).
1257 m.next = "round"
1258 m.d.sync += self.ack.eq(1)
1259 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1260
1261
1262 class FPNormToPack(FPState, FPID):
1263
1264 def __init__(self, width, id_wid):
1265 FPID.__init__(self, id_wid)
1266 FPState.__init__(self, "normalise_1")
1267 self.width = width
1268
1269 def setup(self, m, in_z, in_of, in_mid):
1270 """ links module to inputs and outputs
1271 """
1272
1273 # Normalisation (chained to input in_z+in_of)
1274 nmod = FPNorm1ModSingle(self.width, self.id_wid)
1275 n_out = nmod.ospec()
1276 nmod.setup(m, in_z, in_of, n_out.z)
1277 m.d.comb += n_out.roundz.eq(nmod.o.roundz)
1278
1279 # Rounding (chained to normalisation)
1280 rmod = FPRoundMod(self.width, self.id_wid)
1281 r_out_z = rmod.ospec()
1282 rmod.setup(m, n_out.z, n_out.roundz)
1283 m.d.comb += r_out_z.eq(rmod.out_z)
1284
1285 # Corrections (chained to rounding)
1286 cmod = FPCorrectionsMod(self.width, self.id_wid)
1287 c_out_z = cmod.ospec()
1288 cmod.setup(m, r_out_z)
1289 m.d.comb += c_out_z.eq(cmod.out_z)
1290
1291 # Pack (chained to corrections)
1292 self.pmod = FPPackMod(self.width, self.id_wid)
1293 self.out_z = self.pmod.ospec()
1294 self.pmod.setup(m, c_out_z)
1295
1296 # Multiplex ID
1297 if self.in_mid is not None:
1298 m.d.comb += self.in_mid.eq(in_mid)
1299
1300 def action(self, m):
1301 self.idsync(m) # copies incoming ID to outgoing
1302 m.d.sync += self.out_z.z.v.eq(self.pmod.o.z.v) # outputs packed result
1303 m.next = "pack_put_z"
1304
1305
1306 class FPRoundData:
1307
1308 def __init__(self, width, id_wid):
1309 self.z = FPNumBase(width, False)
1310 self.mid = Signal(id_wid, reset_less=True)
1311
1312 def eq(self, i):
1313 return [self.z.eq(i.z), self.mid.eq(i.mid)]
1314
1315
1316 class FPRoundMod:
1317
1318 def __init__(self, width, id_wid):
1319 self.width = width
1320 self.id_wid = id_wid
1321 self.i = self.ispec()
1322 self.out_z = self.ospec()
1323
1324 def ispec(self):
1325 return FPNorm1Data(self.width, self.id_wid)
1326
1327 def ospec(self):
1328 return FPRoundData(self.width, self.id_wid)
1329
1330 def setup(self, m, in_z, roundz):
1331 m.submodules.roundz = self
1332
1333 m.d.comb += self.i.z.eq(in_z)
1334 m.d.comb += self.i.roundz.eq(roundz)
1335
1336 def elaborate(self, platform):
1337 m = Module()
1338 m.d.comb += self.out_z.eq(self.i)
1339 with m.If(self.i.roundz):
1340 m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa rounds up
1341 with m.If(self.i.z.m == self.i.z.m1s): # all 1s
1342 m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1) # exponent up
1343 return m
1344
1345
1346 class FPRound(FPState, FPID):
1347
1348 def __init__(self, width, id_wid):
1349 FPState.__init__(self, "round")
1350 FPID.__init__(self, id_wid)
1351 self.mod = FPRoundMod(width)
1352 self.out_z = self.mod.ospec()
1353
1354 def setup(self, m, in_z, roundz, in_mid):
1355 """ links module to inputs and outputs
1356 """
1357 self.mod.setup(m, in_z, roundz)
1358
1359 if self.in_mid is not None:
1360 m.d.comb += self.in_mid.eq(in_mid)
1361
1362 def action(self, m):
1363 self.idsync(m)
1364 m.d.sync += self.out_z.eq(self.mod.out_z)
1365 m.next = "corrections"
1366
1367
1368 class FPCorrectionsMod:
1369
1370 def __init__(self, width, id_wid):
1371 self.width = width
1372 self.id_wid = id_wid
1373 self.in_z = self.ispec()
1374 self.out_z = self.ospec()
1375
1376 def ispec(self):
1377 return FPRoundData(self.width, self.id_wid)
1378
1379 def ospec(self):
1380 return FPRoundData(self.width, self.id_wid)
1381
1382 def setup(self, m, in_z):
1383 """ links module to inputs and outputs
1384 """
1385 m.submodules.corrections = self
1386 m.d.comb += self.in_z.eq(in_z)
1387
1388 def elaborate(self, platform):
1389 m = Module()
1390 m.submodules.corr_in_z = self.in_z.z
1391 m.submodules.corr_out_z = self.out_z.z
1392 m.d.comb += self.out_z.eq(self.in_z)
1393 with m.If(self.in_z.z.is_denormalised):
1394 m.d.comb += self.out_z.z.e.eq(self.in_z.z.N127)
1395 return m
1396
1397
1398 class FPCorrections(FPState, FPID):
1399
1400 def __init__(self, width, id_wid):
1401 FPState.__init__(self, "corrections")
1402 FPID.__init__(self, id_wid)
1403 self.mod = FPCorrectionsMod(width)
1404 self.out_z = self.mod.ospec()
1405
1406 def setup(self, m, in_z, in_mid):
1407 """ links module to inputs and outputs
1408 """
1409 self.mod.setup(m, in_z)
1410 if self.in_mid is not None:
1411 m.d.comb += self.in_mid.eq(in_mid)
1412
1413 def action(self, m):
1414 self.idsync(m)
1415 m.d.sync += self.out_z.eq(self.mod.out_z)
1416 m.next = "pack"
1417
1418
1419 class FPPackData:
1420
1421 def __init__(self, width, id_wid):
1422 self.z = FPNumOut(width, False)
1423 self.mid = Signal(id_wid, reset_less=True)
1424
1425 def eq(self, i):
1426 return [self.z.eq(i.z), self.mid.eq(i.mid)]
1427
1428
1429 class FPPackMod:
1430
1431 def __init__(self, width, id_wid):
1432 self.width = width
1433 self.id_wid = id_wid
1434 self.i = self.ispec()
1435 self.o = self.ospec()
1436
1437 def ispec(self):
1438 return FPRoundData(self.width, self.id_wid)
1439
1440 def ospec(self):
1441 return FPPackData(self.width, self.id_wid)
1442
1443 def setup(self, m, in_z):
1444 """ links module to inputs and outputs
1445 """
1446 m.submodules.pack = self
1447 m.d.comb += self.i.eq(in_z)
1448
1449 def elaborate(self, platform):
1450 m = Module()
1451 m.submodules.pack_in_z = self.i.z
1452 with m.If(self.i.z.is_overflowed):
1453 m.d.comb += self.o.z.inf(self.i.z.s)
1454 with m.Else():
1455 m.d.comb += self.o.z.create(self.i.z.s, self.i.z.e, self.i.z.m)
1456 return m
1457
1458
1459 class FPPackData:
1460 def __init__(self, width, id_wid):
1461 self.z = FPNumOut(width, False)
1462 self.mid = Signal(id_wid, reset_less=True)
1463
1464 def eq(self, i):
1465 return [self.z.eq(i.z), self.mid.eq(i.mid)]
1466
1467
1468 class FPPack(FPState, FPID):
1469
1470 def __init__(self, width, id_wid):
1471 FPState.__init__(self, "pack")
1472 FPID.__init__(self, id_wid)
1473 self.mod = FPPackMod(width)
1474 self.out_z = self.ospec()
1475
1476 def ispec(self):
1477 return self.mod.ispec()
1478
1479 def ospec(self):
1480 return self.mod.ospec()
1481
1482 def setup(self, m, in_z, in_mid):
1483 """ links module to inputs and outputs
1484 """
1485 self.mod.setup(m, in_z)
1486 if self.in_mid is not None:
1487 m.d.comb += self.in_mid.eq(in_mid)
1488
1489 def action(self, m):
1490 self.idsync(m)
1491 m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1492 m.next = "pack_put_z"
1493
1494
1495 class FPPutZ(FPState):
1496
1497 def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1498 FPState.__init__(self, state)
1499 if to_state is None:
1500 to_state = "get_ops"
1501 self.to_state = to_state
1502 self.in_z = in_z
1503 self.out_z = out_z
1504 self.in_mid = in_mid
1505 self.out_mid = out_mid
1506
1507 def action(self, m):
1508 if self.in_mid is not None:
1509 m.d.sync += self.out_mid.eq(self.in_mid)
1510 m.d.sync += [
1511 self.out_z.v.eq(self.in_z.v)
1512 ]
1513 with m.If(self.out_z.stb & self.out_z.ack):
1514 m.d.sync += self.out_z.stb.eq(0)
1515 m.next = self.to_state
1516 with m.Else():
1517 m.d.sync += self.out_z.stb.eq(1)
1518
1519
1520 class FPPutZIdx(FPState):
1521
1522 def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1523 FPState.__init__(self, state)
1524 if to_state is None:
1525 to_state = "get_ops"
1526 self.to_state = to_state
1527 self.in_z = in_z
1528 self.out_zs = out_zs
1529 self.in_mid = in_mid
1530
1531 def action(self, m):
1532 outz_stb = Signal(reset_less=True)
1533 outz_ack = Signal(reset_less=True)
1534 m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1535 outz_ack.eq(self.out_zs[self.in_mid].ack),
1536 ]
1537 m.d.sync += [
1538 self.out_zs[self.in_mid].v.eq(self.in_z.v)
1539 ]
1540 with m.If(outz_stb & outz_ack):
1541 m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1542 m.next = self.to_state
1543 with m.Else():
1544 m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1545
1546
1547 class FPADDBaseMod(FPID):
1548
1549 def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1550 """ IEEE754 FP Add
1551
1552 * width: bit-width of IEEE754. supported: 16, 32, 64
1553 * id_wid: an identifier that is sync-connected to the input
1554 * single_cycle: True indicates each stage to complete in 1 clock
1555 * compact: True indicates a reduced number of stages
1556 """
1557 FPID.__init__(self, id_wid)
1558 self.width = width
1559 self.single_cycle = single_cycle
1560 self.compact = compact
1561
1562 self.in_t = Trigger()
1563 self.in_a = Signal(width)
1564 self.in_b = Signal(width)
1565 self.out_z = FPOp(width)
1566
1567 self.states = []
1568
1569 def add_state(self, state):
1570 self.states.append(state)
1571 return state
1572
1573 def get_fragment(self, platform=None):
1574 """ creates the HDL code-fragment for FPAdd
1575 """
1576 m = Module()
1577 m.submodules.out_z = self.out_z
1578 m.submodules.in_t = self.in_t
1579 if self.compact:
1580 self.get_compact_fragment(m, platform)
1581 else:
1582 self.get_longer_fragment(m, platform)
1583
1584 with m.FSM() as fsm:
1585
1586 for state in self.states:
1587 with m.State(state.state_from):
1588 state.action(m)
1589
1590 return m
1591
1592 def get_longer_fragment(self, m, platform=None):
1593
1594 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1595 self.in_a, self.in_b, self.width))
1596 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1597 a = get.out_op1
1598 b = get.out_op2
1599
1600 sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1601 sc.setup(m, a, b, self.in_mid)
1602
1603 dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1604 dn.setup(m, a, b, sc.in_mid)
1605
1606 if self.single_cycle:
1607 alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1608 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1609 else:
1610 alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1611 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1612
1613 add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1614 add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1615
1616 add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1617 add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1618
1619 if self.single_cycle:
1620 n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1621 n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1622 else:
1623 n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1624 n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1625
1626 rn = self.add_state(FPRound(self.width, self.id_wid))
1627 rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1628
1629 cor = self.add_state(FPCorrections(self.width, self.id_wid))
1630 cor.setup(m, rn.out_z, rn.in_mid)
1631
1632 pa = self.add_state(FPPack(self.width, self.id_wid))
1633 pa.setup(m, cor.out_z, rn.in_mid)
1634
1635 ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1636 pa.in_mid, self.out_mid))
1637
1638 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1639 pa.in_mid, self.out_mid))
1640
1641 def get_compact_fragment(self, m, platform=None):
1642
1643 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1644 self.in_a, self.in_b,
1645 self.width, self.id_wid))
1646 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1647 a = get.o.a
1648 b = get.o.b
1649
1650 sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1651 sc.setup(m, a, b, self.in_mid)
1652
1653 alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1654 alm.setup(m, sc.o.a, sc.o.b, sc.in_mid)
1655
1656 n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1657 n1.setup(m, alm.a1o.z, alm.a1o.of, alm.in_mid)
1658
1659 ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z.z, self.out_z,
1660 n1.in_mid, self.out_mid))
1661
1662 pz = self.add_state(FPPutZ("put_z", sc.out_z.z, self.out_z,
1663 sc.in_mid, self.out_mid))
1664
1665
1666 class FPADDBase(FPState, FPID):
1667
1668 def __init__(self, width, id_wid=None, single_cycle=False):
1669 """ IEEE754 FP Add
1670
1671 * width: bit-width of IEEE754. supported: 16, 32, 64
1672 * id_wid: an identifier that is sync-connected to the input
1673 * single_cycle: True indicates each stage to complete in 1 clock
1674 """
1675 FPID.__init__(self, id_wid)
1676 FPState.__init__(self, "fpadd")
1677 self.width = width
1678 self.single_cycle = single_cycle
1679 self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1680
1681 self.in_t = Trigger()
1682 self.in_a = Signal(width)
1683 self.in_b = Signal(width)
1684 #self.out_z = FPOp(width)
1685
1686 self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1687 self.in_accept = Signal(reset_less=True)
1688 self.add_stb = Signal(reset_less=True)
1689 self.add_ack = Signal(reset=0, reset_less=True)
1690
1691 def setup(self, m, a, b, add_stb, in_mid, out_z, out_mid):
1692 self.out_z = out_z
1693 self.out_mid = out_mid
1694 m.d.comb += [self.in_a.eq(a),
1695 self.in_b.eq(b),
1696 self.mod.in_a.eq(self.in_a),
1697 self.mod.in_b.eq(self.in_b),
1698 self.in_mid.eq(in_mid),
1699 self.mod.in_mid.eq(self.in_mid),
1700 self.z_done.eq(self.mod.out_z.trigger),
1701 #self.add_stb.eq(add_stb),
1702 self.mod.in_t.stb.eq(self.in_t.stb),
1703 self.in_t.ack.eq(self.mod.in_t.ack),
1704 self.out_mid.eq(self.mod.out_mid),
1705 self.out_z.v.eq(self.mod.out_z.v),
1706 self.out_z.stb.eq(self.mod.out_z.stb),
1707 self.mod.out_z.ack.eq(self.out_z.ack),
1708 ]
1709
1710 m.d.sync += self.add_stb.eq(add_stb)
1711 m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1712 m.d.sync += self.out_z.ack.eq(0) # likewise
1713 #m.d.sync += self.in_t.stb.eq(0)
1714
1715 m.submodules.fpadd = self.mod
1716
1717 def action(self, m):
1718
1719 # in_accept is set on incoming strobe HIGH and ack LOW.
1720 m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1721
1722 #with m.If(self.in_t.ack):
1723 # m.d.sync += self.in_t.stb.eq(0)
1724 with m.If(~self.z_done):
1725 # not done: test for accepting an incoming operand pair
1726 with m.If(self.in_accept):
1727 m.d.sync += [
1728 self.add_ack.eq(1), # acknowledge receipt...
1729 self.in_t.stb.eq(1), # initiate add
1730 ]
1731 with m.Else():
1732 m.d.sync += [self.add_ack.eq(0),
1733 self.in_t.stb.eq(0),
1734 self.out_z.ack.eq(1),
1735 ]
1736 with m.Else():
1737 # done: acknowledge, and write out id and value
1738 m.d.sync += [self.add_ack.eq(1),
1739 self.in_t.stb.eq(0)
1740 ]
1741 m.next = "put_z"
1742
1743 return
1744
1745 if self.in_mid is not None:
1746 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1747
1748 m.d.sync += [
1749 self.out_z.v.eq(self.mod.out_z.v)
1750 ]
1751 # move to output state on detecting z ack
1752 with m.If(self.out_z.trigger):
1753 m.d.sync += self.out_z.stb.eq(0)
1754 m.next = "put_z"
1755 with m.Else():
1756 m.d.sync += self.out_z.stb.eq(1)
1757
1758 class ResArray:
1759 def __init__(self, width, id_wid):
1760 self.width = width
1761 self.id_wid = id_wid
1762 res = []
1763 for i in range(rs_sz):
1764 out_z = FPOp(width)
1765 out_z.name = "out_z_%d" % i
1766 res.append(out_z)
1767 self.res = Array(res)
1768 self.in_z = FPOp(width)
1769 self.in_mid = Signal(self.id_wid, reset_less=True)
1770
1771 def setup(self, m, in_z, in_mid):
1772 m.d.comb += [self.in_z.eq(in_z),
1773 self.in_mid.eq(in_mid)]
1774
1775 def get_fragment(self, platform=None):
1776 """ creates the HDL code-fragment for FPAdd
1777 """
1778 m = Module()
1779 m.submodules.res_in_z = self.in_z
1780 m.submodules += self.res
1781
1782 return m
1783
1784 def ports(self):
1785 res = []
1786 for z in self.res:
1787 res += z.ports()
1788 return res
1789
1790
1791 class FPADD(FPID):
1792 """ FPADD: stages as follows:
1793
1794 FPGetOp (a)
1795 |
1796 FPGetOp (b)
1797 |
1798 FPAddBase---> FPAddBaseMod
1799 | |
1800 PutZ GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1801
1802 FPAddBase is tricky: it is both a stage and *has* stages.
1803 Connection to FPAddBaseMod therefore requires an in stb/ack
1804 and an out stb/ack. Just as with Add1-Norm1 interaction, FPGetOp
1805 needs to be the thing that raises the incoming stb.
1806 """
1807
1808 def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1809 """ IEEE754 FP Add
1810
1811 * width: bit-width of IEEE754. supported: 16, 32, 64
1812 * id_wid: an identifier that is sync-connected to the input
1813 * single_cycle: True indicates each stage to complete in 1 clock
1814 """
1815 self.width = width
1816 self.id_wid = id_wid
1817 self.single_cycle = single_cycle
1818
1819 #self.out_z = FPOp(width)
1820 self.ids = FPID(id_wid)
1821
1822 rs = []
1823 for i in range(rs_sz):
1824 in_a = FPOp(width)
1825 in_b = FPOp(width)
1826 in_a.name = "in_a_%d" % i
1827 in_b.name = "in_b_%d" % i
1828 rs.append((in_a, in_b))
1829 self.rs = Array(rs)
1830
1831 res = []
1832 for i in range(rs_sz):
1833 out_z = FPOp(width)
1834 out_z.name = "out_z_%d" % i
1835 res.append(out_z)
1836 self.res = Array(res)
1837
1838 self.states = []
1839
1840 def add_state(self, state):
1841 self.states.append(state)
1842 return state
1843
1844 def get_fragment(self, platform=None):
1845 """ creates the HDL code-fragment for FPAdd
1846 """
1847 m = Module()
1848 m.submodules += self.rs
1849
1850 in_a = self.rs[0][0]
1851 in_b = self.rs[0][1]
1852
1853 out_z = FPOp(self.width)
1854 out_mid = Signal(self.id_wid, reset_less=True)
1855 m.submodules.out_z = out_z
1856
1857 geta = self.add_state(FPGetOp("get_a", "get_b",
1858 in_a, self.width))
1859 geta.setup(m, in_a)
1860 a = geta.out_op
1861
1862 getb = self.add_state(FPGetOp("get_b", "fpadd",
1863 in_b, self.width))
1864 getb.setup(m, in_b)
1865 b = getb.out_op
1866
1867 ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1868 ab = self.add_state(ab)
1869 ab.setup(m, a, b, getb.out_decode, self.ids.in_mid,
1870 out_z, out_mid)
1871
1872 pz = self.add_state(FPPutZIdx("put_z", ab.out_z, self.res,
1873 out_mid, "get_a"))
1874
1875 with m.FSM() as fsm:
1876
1877 for state in self.states:
1878 with m.State(state.state_from):
1879 state.action(m)
1880
1881 return m
1882
1883
1884 if __name__ == "__main__":
1885 if True:
1886 alu = FPADD(width=32, id_wid=5, single_cycle=True)
1887 main(alu, ports=alu.rs[0][0].ports() + \
1888 alu.rs[0][1].ports() + \
1889 alu.res[0].ports() + \
1890 [alu.ids.in_mid, alu.ids.out_mid])
1891 else:
1892 alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1893 main(alu, ports=[alu.in_a, alu.in_b] + \
1894 alu.in_t.ports() + \
1895 alu.out_z.ports() + \
1896 [alu.in_mid, alu.out_mid])
1897
1898
1899 # works... but don't use, just do "python fname.py convert -t v"
1900 #print (verilog.convert(alu, ports=[
1901 # ports=alu.in_a.ports() + \
1902 # alu.in_b.ports() + \
1903 # alu.out_z.ports())