src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Mux, Array, Const
   6 from nmigen.lib.coding import PriorityEncoder
   7 from nmigen.cli import main, verilog
   8 from math import log
   9
  10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
  11 from fpbase import MultiShiftRMerge, Trigger
  12 #from fpbase import FPNumShiftMultiRight
  13
  14
  15 class FPState(FPBase):
  16     def __init__(self, state_from):
  17         self.state_from = state_from
  18
  19     def set_inputs(self, inputs):
  20         self.inputs = inputs
  21         for k,v in inputs.items():
  22             setattr(self, k, v)
  23
  24     def set_outputs(self, outputs):
  25         self.outputs = outputs
  26         for k,v in outputs.items():
  27             setattr(self, k, v)
  28
  29
  30 class FPGetSyncOpsMod:
  31     def __init__(self, width, num_ops=2):
  32         self.width = width
  33         self.num_ops = num_ops
  34         inops = []
  35         outops = []
  36         for i in range(num_ops):
  37             inops.append(Signal(width, reset_less=True))
  38             outops.append(Signal(width, reset_less=True))
  39         self.in_op = inops
  40         self.out_op = outops
  41         self.stb = Signal(num_ops)
  42         self.ack = Signal()
  43         self.ready = Signal(reset_less=True)
  44         self.out_decode = Signal(reset_less=True)
  45
  46     def elaborate(self, platform):
  47         m = Module()
  48         m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
  49         m.d.comb += self.out_decode.eq(self.ack & self.ready)
  50         with m.If(self.out_decode):
  51             for i in range(self.num_ops):
  52                 m.d.comb += [
  53                         self.out_op[i].eq(self.in_op[i]),
  54                 ]
  55         return m
  56
  57     def ports(self):
  58         return self.in_op + self.out_op + [self.stb, self.ack]
  59
  60
  61 class FPOps(Trigger):
  62     def __init__(self, width, num_ops):
  63         Trigger.__init__(self)
  64         self.width = width
  65         self.num_ops = num_ops
  66
  67         res = []
  68         for i in range(num_ops):
  69             res.append(Signal(width))
  70         self.v  = Array(res)
  71
  72     def ports(self):
  73         res = []
  74         for i in range(self.num_ops):
  75             res.append(self.v[i])
  76         res.append(self.ack)
  77         res.append(self.stb)
  78         return res
  79
  80
  81 class InputGroup:
  82     def __init__(self, width, num_ops=2, num_rows=4):
  83         self.width = width
  84         self.num_ops = num_ops
  85         self.num_rows = num_rows
  86         self.mmax = int(log(self.num_rows) / log(2))
  87         self.rs = []
  88         self.mid = Signal(self.mmax, reset_less=True) # multiplex id
  89         for i in range(num_rows):
  90             self.rs.append(FPGetSyncOpsMod(width, num_ops))
  91         self.rs = Array(self.rs)
  92
  93         self.out_op = FPOps(width, num_ops)
  94
  95     def elaborate(self, platform):
  96         m = Module()
  97
  98         pe = PriorityEncoder(self.num_rows)
  99         m.submodules.selector = pe
 100         m.submodules.out_op = self.out_op
 101         m.submodules += self.rs
 102
 103         # connect priority encoder
 104         in_ready = []
 105         for i in range(self.num_rows):
 106             in_ready.append(self.rs[i].ready)
 107         m.d.comb += pe.i.eq(Cat(*in_ready))
 108
 109         active = Signal(reset_less=True)
 110         out_en = Signal(reset_less=True)
 111         m.d.comb += active.eq(~pe.n) # encoder active
 112         m.d.comb += out_en.eq(active & self.out_op.trigger)
 113
 114         # encoder active: ack relevant input, record MID, pass output
 115         with m.If(out_en):
 116             rs = self.rs[pe.o]
 117             m.d.sync += self.mid.eq(pe.o)
 118             m.d.sync += rs.ack.eq(0)
 119             m.d.sync += self.out_op.stb.eq(0)
 120             for j in range(self.num_ops):
 121                 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
 122         with m.Else():
 123             m.d.sync += self.out_op.stb.eq(1)
 124             # acks all default to zero
 125             for i in range(self.num_rows):
 126                 m.d.sync += self.rs[i].ack.eq(1)
 127
 128         return m
 129
 130     def ports(self):
 131         res = []
 132         for i in range(self.num_rows):
 133             inop = self.rs[i]
 134             res += inop.in_op + [inop.stb]
 135         return self.out_op.ports() + res + [self.mid]
 136
 137
 138 class FPGetOpMod:
 139     def __init__(self, width):
 140         self.in_op = FPOp(width)
 141         self.out_op = Signal(width)
 142         self.out_decode = Signal(reset_less=True)
 143
 144     def elaborate(self, platform):
 145         m = Module()
 146         m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
 147         m.submodules.get_op_in = self.in_op
 148         #m.submodules.get_op_out = self.out_op
 149         with m.If(self.out_decode):
 150             m.d.comb += [
 151                 self.out_op.eq(self.in_op.v),
 152             ]
 153         return m
 154
 155
 156 class FPGetOp(FPState):
 157     """ gets operand
 158     """
 159
 160     def __init__(self, in_state, out_state, in_op, width):
 161         FPState.__init__(self, in_state)
 162         self.out_state = out_state
 163         self.mod = FPGetOpMod(width)
 164         self.in_op = in_op
 165         self.out_op = Signal(width)
 166         self.out_decode = Signal(reset_less=True)
 167
 168     def setup(self, m, in_op):
 169         """ links module to inputs and outputs
 170         """
 171         setattr(m.submodules, self.state_from, self.mod)
 172         m.d.comb += self.mod.in_op.eq(in_op)
 173         #m.d.comb += self.out_op.eq(self.mod.out_op)
 174         m.d.comb += self.out_decode.eq(self.mod.out_decode)
 175
 176     def action(self, m):
 177         with m.If(self.out_decode):
 178             m.next = self.out_state
 179             m.d.sync += [
 180                 self.in_op.ack.eq(0),
 181                 self.out_op.eq(self.mod.out_op)
 182             ]
 183         with m.Else():
 184             m.d.sync += self.in_op.ack.eq(1)
 185
 186
 187 class FPGet2OpMod(Trigger):
 188     def __init__(self, width, id_wid):
 189         Trigger.__init__(self)
 190         self.width = width
 191         self.id_wid = id_wid
 192         self.i = self.ispec()
 193         self.o = self.ospec()
 194
 195     def ispec(self):
 196         return FPADDBaseData(self.width, self.id_wid)
 197
 198     def ospec(self):
 199         return FPNumBase2Ops(self.width, self.id_wid)
 200
 201     def elaborate(self, platform):
 202         m = Trigger.elaborate(self, platform)
 203         #m.submodules.get_op_in = self.in_op
 204         m.submodules.get_op1_out = self.o.a
 205         m.submodules.get_op2_out = self.o.b
 206         out_op1 = FPNumIn(None, self.width)
 207         out_op2 = FPNumIn(None, self.width)
 208         with m.If(self.trigger):
 209             m.d.comb += [
 210                 out_op1.decode(self.i.a),
 211                 out_op2.decode(self.i.b),
 212                 self.o.a.eq(out_op1),
 213                 self.o.b.eq(out_op2),
 214             ]
 215         return m
 216
 217
 218 class FPGet2Op(FPState):
 219     """ gets operands
 220     """
 221
 222     def __init__(self, in_state, out_state, in_op1, in_op2, width, id_wid):
 223         FPState.__init__(self, in_state)
 224         self.out_state = out_state
 225         self.mod = FPGet2OpMod(width, id_wid)
 226         self.in_op1 = in_op1
 227         self.in_op2 = in_op2
 228         self.o = self.mod.ospec()
 229         self.in_stb = Signal(reset_less=True)
 230         self.out_ack = Signal(reset_less=True)
 231         self.out_decode = Signal(reset_less=True)
 232
 233     def setup(self, m, i, in_stb, in_ack):
 234         """ links module to inputs and outputs
 235         """
 236         m.submodules.get_ops = self.mod
 237         m.d.comb += self.mod.i.eq(i)
 238         m.d.comb += self.mod.stb.eq(in_stb)
 239         m.d.comb += self.out_ack.eq(self.mod.ack)
 240         m.d.comb += self.out_decode.eq(self.mod.trigger)
 241         m.d.comb += in_ack.eq(self.mod.ack)
 242
 243     def action(self, m):
 244         with m.If(self.out_decode):
 245             m.next = self.out_state
 246             m.d.sync += [
 247                 self.mod.ack.eq(0),
 248                 self.o.eq(self.mod.o),
 249             ]
 250         with m.Else():
 251             m.d.sync += self.mod.ack.eq(1)
 252
 253
 254 class FPNumBase2Ops:
 255
 256     def __init__(self, width, id_wid, m_extra=True):
 257         self.a = FPNumBase(width, m_extra)
 258         self.b = FPNumBase(width, m_extra)
 259         self.mid = Signal(id_wid, reset_less=True)
 260
 261     def eq(self, i):
 262         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 263
 264
 265 class FPAddSpecialCasesMod:
 266     """ special cases: NaNs, infs, zeros, denormalised
 267         NOTE: some of these are unique to add.  see "Special Operations"
 268         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 269     """
 270
 271     def __init__(self, width, id_wid):
 272         self.width = width
 273         self.id_wid = id_wid
 274         self.i = self.ispec()
 275         self.o = self.ospec()
 276         self.out_do_z = Signal(reset_less=True)
 277
 278     def ispec(self):
 279         return FPNumBase2Ops(self.width, self.id_wid)
 280
 281     def ospec(self):
 282         return FPPackData(self.width, self.id_wid)
 283
 284     def setup(self, m, i, out_do_z):
 285         """ links module to inputs and outputs
 286         """
 287         m.submodules.specialcases = self
 288         m.d.comb += self.i.eq(i)
 289         m.d.comb += out_do_z.eq(self.out_do_z)
 290
 291     def elaborate(self, platform):
 292         m = Module()
 293
 294         m.submodules.sc_in_a = self.i.a
 295         m.submodules.sc_in_b = self.i.b
 296         m.submodules.sc_out_z = self.o.z
 297
 298         s_nomatch = Signal()
 299         m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
 300
 301         m_match = Signal()
 302         m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
 303
 304         # if a is NaN or b is NaN return NaN
 305         with m.If(self.i.a.is_nan | self.i.b.is_nan):
 306             m.d.comb += self.out_do_z.eq(1)
 307             m.d.comb += self.o.z.nan(0)
 308
 309         # XXX WEIRDNESS for FP16 non-canonical NaN handling
 310         # under review
 311
 312         ## if a is zero and b is NaN return -b
 313         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
 314         #    m.d.comb += self.out_do_z.eq(1)
 315         #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
 316
 317         ## if b is zero and a is NaN return -a
 318         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
 319         #    m.d.comb += self.out_do_z.eq(1)
 320         #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
 321
 322         ## if a is -zero and b is NaN return -b
 323         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
 324         #    m.d.comb += self.out_do_z.eq(1)
 325         #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
 326
 327         ## if b is -zero and a is NaN return -a
 328         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 329         #    m.d.comb += self.out_do_z.eq(1)
 330         #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 331
 332         # if a is inf return inf (or NaN)
 333         with m.Elif(self.i.a.is_inf):
 334             m.d.comb += self.out_do_z.eq(1)
 335             m.d.comb += self.o.z.inf(self.i.a.s)
 336             # if a is inf and signs don't match return NaN
 337             with m.If(self.i.b.exp_128 & s_nomatch):
 338                 m.d.comb += self.o.z.nan(0)
 339
 340         # if b is inf return inf
 341         with m.Elif(self.i.b.is_inf):
 342             m.d.comb += self.out_do_z.eq(1)
 343             m.d.comb += self.o.z.inf(self.i.b.s)
 344
 345         # if a is zero and b zero return signed-a/b
 346         with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
 347             m.d.comb += self.out_do_z.eq(1)
 348             m.d.comb += self.o.z.create(self.i.a.s & self.i.b.s,
 349                                           self.i.b.e,
 350                                           self.i.b.m[3:-1])
 351
 352         # if a is zero return b
 353         with m.Elif(self.i.a.is_zero):
 354             m.d.comb += self.out_do_z.eq(1)
 355             m.d.comb += self.o.z.create(self.i.b.s, self.i.b.e,
 356                                       self.i.b.m[3:-1])
 357
 358         # if b is zero return a
 359         with m.Elif(self.i.b.is_zero):
 360             m.d.comb += self.out_do_z.eq(1)
 361             m.d.comb += self.o.z.create(self.i.a.s, self.i.a.e,
 362                                       self.i.a.m[3:-1])
 363
 364         # if a equal to -b return zero (+ve zero)
 365         with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
 366             m.d.comb += self.out_do_z.eq(1)
 367             m.d.comb += self.o.z.zero(0)
 368
 369         # Denormalised Number checks
 370         with m.Else():
 371             m.d.comb += self.out_do_z.eq(0)
 372
 373         return m
 374
 375
 376 class FPID:
 377     def __init__(self, id_wid):
 378         self.id_wid = id_wid
 379         if self.id_wid:
 380             self.in_mid = Signal(id_wid, reset_less=True)
 381             self.out_mid = Signal(id_wid, reset_less=True)
 382         else:
 383             self.in_mid = None
 384             self.out_mid = None
 385
 386     def idsync(self, m):
 387         if self.id_wid is not None:
 388             m.d.sync += self.out_mid.eq(self.in_mid)
 389
 390
 391 class FPAddSpecialCases(FPState, FPID):
 392     """ special cases: NaNs, infs, zeros, denormalised
 393         NOTE: some of these are unique to add.  see "Special Operations"
 394         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 395     """
 396
 397     def __init__(self, width, id_wid):
 398         FPState.__init__(self, "special_cases")
 399         FPID.__init__(self, id_wid)
 400         self.mod = FPAddSpecialCasesMod(width)
 401         self.out_z = self.mod.ospec()
 402         self.out_do_z = Signal(reset_less=True)
 403
 404     def setup(self, m, in_a, in_b, in_mid):
 405         """ links module to inputs and outputs
 406         """
 407         self.mod.setup(m, in_a, in_b, self.out_do_z)
 408         if self.in_mid is not None:
 409             m.d.comb += self.in_mid.eq(in_mid)
 410
 411     def action(self, m):
 412         self.idsync(m)
 413         with m.If(self.out_do_z):
 414             m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
 415             m.next = "put_z"
 416         with m.Else():
 417             m.next = "denormalise"
 418
 419
 420 class FPAddSpecialCasesDeNorm(FPState, FPID):
 421     """ special cases: NaNs, infs, zeros, denormalised
 422         NOTE: some of these are unique to add.  see "Special Operations"
 423         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 424     """
 425
 426     def __init__(self, width, id_wid):
 427         FPState.__init__(self, "special_cases")
 428         FPID.__init__(self, id_wid)
 429         self.smod = FPAddSpecialCasesMod(width, id_wid)
 430         self.out_z = self.smod.ospec()
 431         self.out_do_z = Signal(reset_less=True)
 432
 433         self.dmod = FPAddDeNormMod(width, id_wid)
 434         self.o = self.dmod.ospec()
 435
 436     def setup(self, m, i, in_mid):
 437         """ links module to inputs and outputs
 438         """
 439         self.smod.setup(m, i, self.out_do_z)
 440         self.dmod.setup(m, i)
 441         if self.in_mid is not None:
 442             m.d.comb += self.in_mid.eq(in_mid)
 443
 444     def action(self, m):
 445         self.idsync(m)
 446         with m.If(self.out_do_z):
 447             m.d.sync += self.out_z.z.v.eq(self.smod.o.z.v) # only take output
 448             m.next = "put_z"
 449         with m.Else():
 450             m.next = "align"
 451             m.d.sync += self.o.a.eq(self.dmod.o.a)
 452             m.d.sync += self.o.b.eq(self.dmod.o.b)
 453
 454
 455 class FPAddDeNormMod(FPState):
 456
 457     def __init__(self, width, id_wid):
 458         self.width = width
 459         self.id_wid = id_wid
 460         self.i = self.ispec()
 461         self.o = self.ospec()
 462
 463     def ispec(self):
 464         return FPNumBase2Ops(self.width, self.id_wid)
 465
 466     def ospec(self):
 467         return FPNumBase2Ops(self.width, self.id_wid)
 468
 469     def setup(self, m, i):
 470         """ links module to inputs and outputs
 471         """
 472         m.submodules.denormalise = self
 473         m.d.comb += self.i.eq(i)
 474
 475     def elaborate(self, platform):
 476         m = Module()
 477         m.submodules.denorm_in_a = self.i.a
 478         m.submodules.denorm_in_b = self.i.b
 479         m.submodules.denorm_out_a = self.o.a
 480         m.submodules.denorm_out_b = self.o.b
 481         # hmmm, don't like repeating identical code
 482         m.d.comb += self.o.a.eq(self.i.a)
 483         with m.If(self.i.a.exp_n127):
 484             m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
 485         with m.Else():
 486             m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
 487
 488         m.d.comb += self.o.b.eq(self.i.b)
 489         with m.If(self.i.b.exp_n127):
 490             m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
 491         with m.Else():
 492             m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
 493
 494         return m
 495
 496
 497 class FPAddDeNorm(FPState, FPID):
 498
 499     def __init__(self, width, id_wid):
 500         FPState.__init__(self, "denormalise")
 501         FPID.__init__(self, id_wid)
 502         self.mod = FPAddDeNormMod(width)
 503         self.out_a = FPNumBase(width)
 504         self.out_b = FPNumBase(width)
 505
 506     def setup(self, m, in_a, in_b, in_mid):
 507         """ links module to inputs and outputs
 508         """
 509         self.mod.setup(m, in_a, in_b)
 510         if self.in_mid is not None:
 511             m.d.comb += self.in_mid.eq(in_mid)
 512
 513     def action(self, m):
 514         self.idsync(m)
 515         # Denormalised Number checks
 516         m.next = "align"
 517         m.d.sync += self.out_a.eq(self.mod.out_a)
 518         m.d.sync += self.out_b.eq(self.mod.out_b)
 519
 520
 521 class FPAddAlignMultiMod(FPState):
 522
 523     def __init__(self, width):
 524         self.in_a = FPNumBase(width)
 525         self.in_b = FPNumBase(width)
 526         self.out_a = FPNumIn(None, width)
 527         self.out_b = FPNumIn(None, width)
 528         self.exp_eq = Signal(reset_less=True)
 529
 530     def elaborate(self, platform):
 531         # This one however (single-cycle) will do the shift
 532         # in one go.
 533
 534         m = Module()
 535
 536         m.submodules.align_in_a = self.in_a
 537         m.submodules.align_in_b = self.in_b
 538         m.submodules.align_out_a = self.out_a
 539         m.submodules.align_out_b = self.out_b
 540
 541         # NOTE: this does *not* do single-cycle multi-shifting,
 542         #       it *STAYS* in the align state until exponents match
 543
 544         # exponent of a greater than b: shift b down
 545         m.d.comb += self.exp_eq.eq(0)
 546         m.d.comb += self.out_a.eq(self.in_a)
 547         m.d.comb += self.out_b.eq(self.in_b)
 548         agtb = Signal(reset_less=True)
 549         altb = Signal(reset_less=True)
 550         m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
 551         m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
 552         with m.If(agtb):
 553             m.d.comb += self.out_b.shift_down(self.in_b)
 554         # exponent of b greater than a: shift a down
 555         with m.Elif(altb):
 556             m.d.comb += self.out_a.shift_down(self.in_a)
 557         # exponents equal: move to next stage.
 558         with m.Else():
 559             m.d.comb += self.exp_eq.eq(1)
 560         return m
 561
 562
 563 class FPAddAlignMulti(FPState, FPID):
 564
 565     def __init__(self, width, id_wid):
 566         FPID.__init__(self, id_wid)
 567         FPState.__init__(self, "align")
 568         self.mod = FPAddAlignMultiMod(width)
 569         self.out_a = FPNumIn(None, width)
 570         self.out_b = FPNumIn(None, width)
 571         self.exp_eq = Signal(reset_less=True)
 572
 573     def setup(self, m, in_a, in_b, in_mid):
 574         """ links module to inputs and outputs
 575         """
 576         m.submodules.align = self.mod
 577         m.d.comb += self.mod.in_a.eq(in_a)
 578         m.d.comb += self.mod.in_b.eq(in_b)
 579         #m.d.comb += self.out_a.eq(self.mod.out_a)
 580         #m.d.comb += self.out_b.eq(self.mod.out_b)
 581         m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
 582         if self.in_mid is not None:
 583             m.d.comb += self.in_mid.eq(in_mid)
 584
 585     def action(self, m):
 586         self.idsync(m)
 587         m.d.sync += self.out_a.eq(self.mod.out_a)
 588         m.d.sync += self.out_b.eq(self.mod.out_b)
 589         with m.If(self.exp_eq):
 590             m.next = "add_0"
 591
 592
 593 class FPNumIn2Ops:
 594
 595     def __init__(self, width, id_wid):
 596         self.a = FPNumIn(None, width)
 597         self.b = FPNumIn(None, width)
 598         self.mid = Signal(id_wid, reset_less=True)
 599
 600     def eq(self, i):
 601         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 602
 603
 604 class FPAddAlignSingleMod:
 605
 606     def __init__(self, width, id_wid):
 607         self.width = width
 608         self.id_wid = id_wid
 609         self.i = self.ispec()
 610         self.o = self.ospec()
 611
 612     def ispec(self):
 613         return FPNumBase2Ops(self.width, self.id_wid)
 614
 615     def ospec(self):
 616         return FPNumIn2Ops(self.width, self.id_wid)
 617
 618     def setup(self, m, i):
 619         """ links module to inputs and outputs
 620         """
 621         m.submodules.align = self
 622         m.d.comb += self.i.eq(i)
 623
 624     def elaborate(self, platform):
 625         """ Aligns A against B or B against A, depending on which has the
 626             greater exponent.  This is done in a *single* cycle using
 627             variable-width bit-shift
 628
 629             the shifter used here is quite expensive in terms of gates.
 630             Mux A or B in (and out) into temporaries, as only one of them
 631             needs to be aligned against the other
 632         """
 633         m = Module()
 634
 635         m.submodules.align_in_a = self.i.a
 636         m.submodules.align_in_b = self.i.b
 637         m.submodules.align_out_a = self.o.a
 638         m.submodules.align_out_b = self.o.b
 639
 640         # temporary (muxed) input and output to be shifted
 641         t_inp = FPNumBase(self.width)
 642         t_out = FPNumIn(None, self.width)
 643         espec = (len(self.i.a.e), True)
 644         msr = MultiShiftRMerge(self.i.a.m_width, espec)
 645         m.submodules.align_t_in = t_inp
 646         m.submodules.align_t_out = t_out
 647         m.submodules.multishift_r = msr
 648
 649         ediff = Signal(espec, reset_less=True)
 650         ediffr = Signal(espec, reset_less=True)
 651         tdiff = Signal(espec, reset_less=True)
 652         elz = Signal(reset_less=True)
 653         egz = Signal(reset_less=True)
 654
 655         # connect multi-shifter to t_inp/out mantissa (and tdiff)
 656         m.d.comb += msr.inp.eq(t_inp.m)
 657         m.d.comb += msr.diff.eq(tdiff)
 658         m.d.comb += t_out.m.eq(msr.m)
 659         m.d.comb += t_out.e.eq(t_inp.e + tdiff)
 660         m.d.comb += t_out.s.eq(t_inp.s)
 661
 662         m.d.comb += ediff.eq(self.i.a.e - self.i.b.e)
 663         m.d.comb += ediffr.eq(self.i.b.e - self.i.a.e)
 664         m.d.comb += elz.eq(self.i.a.e < self.i.b.e)
 665         m.d.comb += egz.eq(self.i.a.e > self.i.b.e)
 666
 667         # default: A-exp == B-exp, A and B untouched (fall through)
 668         m.d.comb += self.o.a.eq(self.i.a)
 669         m.d.comb += self.o.b.eq(self.i.b)
 670         # only one shifter (muxed)
 671         #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
 672         # exponent of a greater than b: shift b down
 673         with m.If(egz):
 674             m.d.comb += [t_inp.eq(self.i.b),
 675                          tdiff.eq(ediff),
 676                          self.o.b.eq(t_out),
 677                          self.o.b.s.eq(self.i.b.s), # whoops forgot sign
 678                         ]
 679         # exponent of b greater than a: shift a down
 680         with m.Elif(elz):
 681             m.d.comb += [t_inp.eq(self.i.a),
 682                          tdiff.eq(ediffr),
 683                          self.o.a.eq(t_out),
 684                          self.o.a.s.eq(self.i.a.s), # whoops forgot sign
 685                         ]
 686         return m
 687
 688
 689 class FPAddAlignSingle(FPState, FPID):
 690
 691     def __init__(self, width, id_wid):
 692         FPState.__init__(self, "align")
 693         FPID.__init__(self, id_wid)
 694         self.mod = FPAddAlignSingleMod(width, id_wid)
 695         self.out_a = FPNumIn(None, width)
 696         self.out_b = FPNumIn(None, width)
 697
 698     def setup(self, m, in_a, in_b, in_mid):
 699         """ links module to inputs and outputs
 700         """
 701         self.mod.setup(m, in_a, in_b)
 702         if self.in_mid is not None:
 703             m.d.comb += self.in_mid.eq(in_mid)
 704
 705     def action(self, m):
 706         self.idsync(m)
 707         # NOTE: could be done as comb
 708         m.d.sync += self.out_a.eq(self.mod.out_a)
 709         m.d.sync += self.out_b.eq(self.mod.out_b)
 710         m.next = "add_0"
 711
 712
 713 class FPAddAlignSingleAdd(FPState, FPID):
 714
 715     def __init__(self, width, id_wid):
 716         FPState.__init__(self, "align")
 717         FPID.__init__(self, id_wid)
 718         self.mod = FPAddAlignSingleMod(width, id_wid)
 719         self.o = self.mod.ospec()
 720
 721         self.a0mod = FPAddStage0Mod(width, id_wid)
 722         self.a0o = self.a0mod.ospec()
 723
 724         self.a1mod = FPAddStage1Mod(width, id_wid)
 725         self.a1o = self.a1mod.ospec()
 726
 727     def setup(self, m, i, in_mid):
 728         """ links module to inputs and outputs
 729         """
 730         self.mod.setup(m, i)
 731         m.d.comb += self.o.eq(self.mod.o)
 732
 733         self.a0mod.setup(m, self.o)
 734         m.d.comb += self.a0o.eq(self.a0mod.o)
 735
 736         self.a1mod.setup(m, self.a0o.tot, self.a0o.z)
 737
 738         if self.in_mid is not None:
 739             m.d.comb += self.in_mid.eq(in_mid)
 740
 741     def action(self, m):
 742         self.idsync(m)
 743         m.d.sync += self.a1o.eq(self.a1mod.o)
 744         m.next = "normalise_1"
 745
 746
 747 class FPAddStage0Data:
 748
 749     def __init__(self, width, id_wid):
 750         self.z = FPNumBase(width, False)
 751         self.tot = Signal(self.z.m_width + 4, reset_less=True)
 752         self.mid = Signal(id_wid, reset_less=True)
 753
 754     def eq(self, i):
 755         return [self.z.eq(i.z), self.tot.eq(i.tot), self.mid.eq(i.mid)]
 756
 757
 758 class FPAddStage0Mod:
 759
 760     def __init__(self, width, id_wid):
 761         self.width = width
 762         self.id_wid = id_wid
 763         self.i = self.ispec()
 764         self.o = self.ospec()
 765
 766     def ispec(self):
 767         return FPNumBase2Ops(self.width, self.id_wid)
 768
 769     def ospec(self):
 770         return FPAddStage0Data(self.width, self.id_wid)
 771
 772     def setup(self, m, i):
 773         """ links module to inputs and outputs
 774         """
 775         m.submodules.add0 = self
 776         m.d.comb += self.i.eq(i)
 777
 778     def elaborate(self, platform):
 779         m = Module()
 780         m.submodules.add0_in_a = self.i.a
 781         m.submodules.add0_in_b = self.i.b
 782         m.submodules.add0_out_z = self.o.z
 783
 784         m.d.comb += self.o.z.e.eq(self.i.a.e)
 785
 786         # store intermediate tests (and zero-extended mantissas)
 787         seq = Signal(reset_less=True)
 788         mge = Signal(reset_less=True)
 789         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
 790         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
 791         m.d.comb += [seq.eq(self.i.a.s == self.i.b.s),
 792                      mge.eq(self.i.a.m >= self.i.b.m),
 793                      am0.eq(Cat(self.i.a.m, 0)),
 794                      bm0.eq(Cat(self.i.b.m, 0))
 795                     ]
 796         # same-sign (both negative or both positive) add mantissas
 797         with m.If(seq):
 798             m.d.comb += [
 799                 self.o.tot.eq(am0 + bm0),
 800                 self.o.z.s.eq(self.i.a.s)
 801             ]
 802         # a mantissa greater than b, use a
 803         with m.Elif(mge):
 804             m.d.comb += [
 805                 self.o.tot.eq(am0 - bm0),
 806                 self.o.z.s.eq(self.i.a.s)
 807             ]
 808         # b mantissa greater than a, use b
 809         with m.Else():
 810             m.d.comb += [
 811                 self.o.tot.eq(bm0 - am0),
 812                 self.o.z.s.eq(self.i.b.s)
 813         ]
 814         return m
 815
 816
 817 class FPAddStage0(FPState, FPID):
 818     """ First stage of add.  covers same-sign (add) and subtract
 819         special-casing when mantissas are greater or equal, to
 820         give greatest accuracy.
 821     """
 822
 823     def __init__(self, width, id_wid):
 824         FPState.__init__(self, "add_0")
 825         FPID.__init__(self, id_wid)
 826         self.mod = FPAddStage0Mod(width)
 827         self.o = self.mod.ospec()
 828
 829     def setup(self, m, in_a, in_b, in_mid):
 830         """ links module to inputs and outputs
 831         """
 832         self.mod.setup(m, in_a, in_b)
 833         if self.in_mid is not None:
 834             m.d.comb += self.in_mid.eq(in_mid)
 835
 836     def action(self, m):
 837         self.idsync(m)
 838         # NOTE: these could be done as combinatorial (merge add0+add1)
 839         m.d.sync += self.o.eq(self.mod.o)
 840         m.next = "add_1"
 841
 842
 843 class FPAddStage1Data:
 844
 845     def __init__(self, width, id_wid):
 846         self.z = FPNumBase(width, False)
 847         self.of = Overflow()
 848         self.mid = Signal(id_wid, reset_less=True)
 849
 850     def eq(self, i):
 851         return [self.z.eq(i.z), self.of.eq(i.of), self.mid.eq(i.mid)]
 852
 853
 854
 855 class FPAddStage1Mod(FPState):
 856     """ Second stage of add: preparation for normalisation.
 857         detects when tot sum is too big (tot[27] is kinda a carry bit)
 858     """
 859
 860     def __init__(self, width, id_wid):
 861         self.width = width
 862         self.id_wid = id_wid
 863         self.i = self.ispec()
 864         self.o = self.ospec()
 865
 866     def ispec(self):
 867         return FPAddStage0Data(self.width, self.id_wid)
 868
 869     def ospec(self):
 870         return FPAddStage1Data(self.width, self.id_wid)
 871
 872     def setup(self, m, in_tot, in_z):
 873         """ links module to inputs and outputs
 874         """
 875         m.submodules.add1 = self
 876         m.submodules.add1_out_overflow = self.o.of
 877
 878         m.d.comb += self.i.z.eq(in_z)
 879         m.d.comb += self.i.tot.eq(in_tot)
 880
 881     def elaborate(self, platform):
 882         m = Module()
 883         #m.submodules.norm1_in_overflow = self.in_of
 884         #m.submodules.norm1_out_overflow = self.out_of
 885         #m.submodules.norm1_in_z = self.in_z
 886         #m.submodules.norm1_out_z = self.out_z
 887         m.d.comb += self.o.z.eq(self.i.z)
 888         # tot[-1] (MSB) gets set when the sum overflows. shift result down
 889         with m.If(self.i.tot[-1]):
 890             m.d.comb += [
 891                 self.o.z.m.eq(self.i.tot[4:]),
 892                 self.o.of.m0.eq(self.i.tot[4]),
 893                 self.o.of.guard.eq(self.i.tot[3]),
 894                 self.o.of.round_bit.eq(self.i.tot[2]),
 895                 self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
 896                 self.o.z.e.eq(self.i.z.e + 1)
 897         ]
 898         # tot[-1] (MSB) zero case
 899         with m.Else():
 900             m.d.comb += [
 901                 self.o.z.m.eq(self.i.tot[3:]),
 902                 self.o.of.m0.eq(self.i.tot[3]),
 903                 self.o.of.guard.eq(self.i.tot[2]),
 904                 self.o.of.round_bit.eq(self.i.tot[1]),
 905                 self.o.of.sticky.eq(self.i.tot[0])
 906         ]
 907         return m
 908
 909
 910 class FPAddStage1(FPState, FPID):
 911
 912     def __init__(self, width, id_wid):
 913         FPState.__init__(self, "add_1")
 914         FPID.__init__(self, id_wid)
 915         self.mod = FPAddStage1Mod(width)
 916         self.out_z = FPNumBase(width, False)
 917         self.out_of = Overflow()
 918         self.norm_stb = Signal()
 919
 920     def setup(self, m, in_tot, in_z, in_mid):
 921         """ links module to inputs and outputs
 922         """
 923         self.mod.setup(m, in_tot, in_z)
 924
 925         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
 926
 927         if self.in_mid is not None:
 928             m.d.comb += self.in_mid.eq(in_mid)
 929
 930     def action(self, m):
 931         self.idsync(m)
 932         m.d.sync += self.out_of.eq(self.mod.out_of)
 933         m.d.sync += self.out_z.eq(self.mod.out_z)
 934         m.d.sync += self.norm_stb.eq(1)
 935         m.next = "normalise_1"
 936
 937
 938 class FPNormaliseModSingle:
 939
 940     def __init__(self, width):
 941         self.width = width
 942         self.in_z = self.ispec()
 943         self.out_z = self.ospec()
 944
 945     def ispec(self):
 946         return FPNumBase(self.width, False)
 947
 948     def ospec(self):
 949         return FPNumBase(self.width, False)
 950
 951     def setup(self, m, in_z, out_z):
 952         """ links module to inputs and outputs
 953         """
 954         m.submodules.normalise = self
 955         m.d.comb += self.in_z.eq(in_z)
 956         m.d.comb += out_z.eq(self.out_z)
 957
 958     def elaborate(self, platform):
 959         m = Module()
 960
 961         mwid = self.out_z.m_width+2
 962         pe = PriorityEncoder(mwid)
 963         m.submodules.norm_pe = pe
 964
 965         m.submodules.norm1_out_z = self.out_z
 966         m.submodules.norm1_in_z = self.in_z
 967
 968         in_z = FPNumBase(self.width, False)
 969         in_of = Overflow()
 970         m.submodules.norm1_insel_z = in_z
 971         m.submodules.norm1_insel_overflow = in_of
 972
 973         espec = (len(in_z.e), True)
 974         ediff_n126 = Signal(espec, reset_less=True)
 975         msr = MultiShiftRMerge(mwid, espec)
 976         m.submodules.multishift_r = msr
 977
 978         m.d.comb += in_z.eq(self.in_z)
 979         m.d.comb += in_of.eq(self.in_of)
 980         # initialise out from in (overridden below)
 981         m.d.comb += self.out_z.eq(in_z)
 982         m.d.comb += self.out_of.eq(in_of)
 983         # normalisation decrease condition
 984         decrease = Signal(reset_less=True)
 985         m.d.comb += decrease.eq(in_z.m_msbzero)
 986         # decrease exponent
 987         with m.If(decrease):
 988             # *sigh* not entirely obvious: count leading zeros (clz)
 989             # with a PriorityEncoder: to find from the MSB
 990             # we reverse the order of the bits.
 991             temp_m = Signal(mwid, reset_less=True)
 992             temp_s = Signal(mwid+1, reset_less=True)
 993             clz = Signal((len(in_z.e), True), reset_less=True)
 994             m.d.comb += [
 995                 # cat round and guard bits back into the mantissa
 996                 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
 997                 pe.i.eq(temp_m[::-1]),          # inverted
 998                 clz.eq(pe.o),                   # count zeros from MSB down
 999                 temp_s.eq(temp_m << clz),       # shift mantissa UP
1000                 self.out_z.e.eq(in_z.e - clz),  # DECREASE exponent
1001                 self.out_z.m.eq(temp_s[2:]),    # exclude bits 0&1
1002             ]
1003
1004         return m
1005
1006 class FPNorm1Data:
1007
1008     def __init__(self, width, id_wid):
1009         self.roundz = Signal(reset_less=True)
1010         self.z = FPNumBase(width, False)
1011         self.mid = Signal(id_wid, reset_less=True)
1012
1013     def eq(self, i):
1014         return [self.z.eq(i.z), self.roundz.eq(i.roundz), self.mid.eq(i.mid)]
1015
1016
1017 class FPNorm1ModSingle:
1018
1019     def __init__(self, width, id_wid):
1020         self.width = width
1021         self.id_wid = id_wid
1022         self.i = self.ispec()
1023         self.o = self.ospec()
1024
1025     def ispec(self):
1026         return FPAddStage1Data(self.width, self.id_wid)
1027
1028     def ospec(self):
1029         return FPNorm1Data(self.width, self.id_wid)
1030
1031     def setup(self, m, i, out_z):
1032         """ links module to inputs and outputs
1033         """
1034         m.submodules.normalise_1 = self
1035
1036         m.d.comb += self.i.eq(i)
1037
1038         m.d.comb += out_z.eq(self.o.z)
1039
1040     def elaborate(self, platform):
1041         m = Module()
1042
1043         mwid = self.o.z.m_width+2
1044         pe = PriorityEncoder(mwid)
1045         m.submodules.norm_pe = pe
1046
1047         of = Overflow()
1048         m.d.comb += self.o.roundz.eq(of.roundz)
1049
1050         m.submodules.norm1_out_z = self.o.z
1051         m.submodules.norm1_out_overflow = of
1052         m.submodules.norm1_in_z = self.i.z
1053         m.submodules.norm1_in_overflow = self.i.of
1054
1055         i = self.ispec()
1056         m.submodules.norm1_insel_z = i.z
1057         m.submodules.norm1_insel_overflow = i.of
1058
1059         espec = (len(i.z.e), True)
1060         ediff_n126 = Signal(espec, reset_less=True)
1061         msr = MultiShiftRMerge(mwid, espec)
1062         m.submodules.multishift_r = msr
1063
1064         m.d.comb += i.eq(self.i)
1065         # initialise out from in (overridden below)
1066         m.d.comb += self.o.z.eq(i.z)
1067         m.d.comb += of.eq(i.of)
1068         # normalisation increase/decrease conditions
1069         decrease = Signal(reset_less=True)
1070         increase = Signal(reset_less=True)
1071         m.d.comb += decrease.eq(i.z.m_msbzero & i.z.exp_gt_n126)
1072         m.d.comb += increase.eq(i.z.exp_lt_n126)
1073         # decrease exponent
1074         with m.If(decrease):
1075             # *sigh* not entirely obvious: count leading zeros (clz)
1076             # with a PriorityEncoder: to find from the MSB
1077             # we reverse the order of the bits.
1078             temp_m = Signal(mwid, reset_less=True)
1079             temp_s = Signal(mwid+1, reset_less=True)
1080             clz = Signal((len(i.z.e), True), reset_less=True)
1081             # make sure that the amount to decrease by does NOT
1082             # go below the minimum non-INF/NaN exponent
1083             limclz = Mux(i.z.exp_sub_n126 > pe.o, pe.o,
1084                          i.z.exp_sub_n126)
1085             m.d.comb += [
1086                 # cat round and guard bits back into the mantissa
1087                 temp_m.eq(Cat(i.of.round_bit, i.of.guard, i.z.m)),
1088                 pe.i.eq(temp_m[::-1]),          # inverted
1089                 clz.eq(limclz),                 # count zeros from MSB down
1090                 temp_s.eq(temp_m << clz),       # shift mantissa UP
1091                 self.o.z.e.eq(i.z.e - clz),  # DECREASE exponent
1092                 self.o.z.m.eq(temp_s[2:]),    # exclude bits 0&1
1093                 of.m0.eq(temp_s[2]),          # copy of mantissa[0]
1094                 # overflow in bits 0..1: got shifted too (leave sticky)
1095                 of.guard.eq(temp_s[1]),       # guard
1096                 of.round_bit.eq(temp_s[0]),   # round
1097             ]
1098         # increase exponent
1099         with m.Elif(increase):
1100             temp_m = Signal(mwid+1, reset_less=True)
1101             m.d.comb += [
1102                 temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
1103                               i.z.m)),
1104                 ediff_n126.eq(i.z.N126 - i.z.e),
1105                 # connect multi-shifter to inp/out mantissa (and ediff)
1106                 msr.inp.eq(temp_m),
1107                 msr.diff.eq(ediff_n126),
1108                 self.o.z.m.eq(msr.m[3:]),
1109                 of.m0.eq(temp_s[3]),   # copy of mantissa[0]
1110                 # overflow in bits 0..1: got shifted too (leave sticky)
1111                 of.guard.eq(temp_s[2]),     # guard
1112                 of.round_bit.eq(temp_s[1]), # round
1113                 of.sticky.eq(temp_s[0]),    # sticky
1114                 self.o.z.e.eq(i.z.e + ediff_n126),
1115             ]
1116
1117         return m
1118
1119
1120 class FPNorm1ModMulti:
1121
1122     def __init__(self, width, single_cycle=True):
1123         self.width = width
1124         self.in_select = Signal(reset_less=True)
1125         self.in_z = FPNumBase(width, False)
1126         self.in_of = Overflow()
1127         self.temp_z = FPNumBase(width, False)
1128         self.temp_of = Overflow()
1129         self.out_z = FPNumBase(width, False)
1130         self.out_of = Overflow()
1131
1132     def elaborate(self, platform):
1133         m = Module()
1134
1135         m.submodules.norm1_out_z = self.out_z
1136         m.submodules.norm1_out_overflow = self.out_of
1137         m.submodules.norm1_temp_z = self.temp_z
1138         m.submodules.norm1_temp_of = self.temp_of
1139         m.submodules.norm1_in_z = self.in_z
1140         m.submodules.norm1_in_overflow = self.in_of
1141
1142         in_z = FPNumBase(self.width, False)
1143         in_of = Overflow()
1144         m.submodules.norm1_insel_z = in_z
1145         m.submodules.norm1_insel_overflow = in_of
1146
1147         # select which of temp or in z/of to use
1148         with m.If(self.in_select):
1149             m.d.comb += in_z.eq(self.in_z)
1150             m.d.comb += in_of.eq(self.in_of)
1151         with m.Else():
1152             m.d.comb += in_z.eq(self.temp_z)
1153             m.d.comb += in_of.eq(self.temp_of)
1154         # initialise out from in (overridden below)
1155         m.d.comb += self.out_z.eq(in_z)
1156         m.d.comb += self.out_of.eq(in_of)
1157         # normalisation increase/decrease conditions
1158         decrease = Signal(reset_less=True)
1159         increase = Signal(reset_less=True)
1160         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1161         m.d.comb += increase.eq(in_z.exp_lt_n126)
1162         m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1163         # decrease exponent
1164         with m.If(decrease):
1165             m.d.comb += [
1166                 self.out_z.e.eq(in_z.e - 1),  # DECREASE exponent
1167                 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1168                 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1169                 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1170                 self.out_of.round_bit.eq(0),        # reset round bit
1171                 self.out_of.m0.eq(in_of.guard),
1172             ]
1173         # increase exponent
1174         with m.Elif(increase):
1175             m.d.comb += [
1176                 self.out_z.e.eq(in_z.e + 1),  # INCREASE exponent
1177                 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1178                 self.out_of.guard.eq(in_z.m[0]),
1179                 self.out_of.m0.eq(in_z.m[1]),
1180                 self.out_of.round_bit.eq(in_of.guard),
1181                 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1182             ]
1183
1184         return m
1185
1186
1187 class FPNorm1Single(FPState, FPID):
1188
1189     def __init__(self, width, id_wid, single_cycle=True):
1190         FPID.__init__(self, id_wid)
1191         FPState.__init__(self, "normalise_1")
1192         self.mod = FPNorm1ModSingle(width)
1193         self.out_z = FPNumBase(width, False)
1194         self.out_roundz = Signal(reset_less=True)
1195
1196     def setup(self, m, in_z, in_of, in_mid):
1197         """ links module to inputs and outputs
1198         """
1199         self.mod.setup(m, in_z, in_of, self.out_z)
1200
1201         if self.in_mid is not None:
1202             m.d.comb += self.in_mid.eq(in_mid)
1203
1204     def action(self, m):
1205         self.idsync(m)
1206         m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1207         m.next = "round"
1208
1209
1210 class FPNorm1Multi(FPState, FPID):
1211
1212     def __init__(self, width, id_wid):
1213         FPID.__init__(self, id_wid)
1214         FPState.__init__(self, "normalise_1")
1215         self.mod = FPNorm1ModMulti(width)
1216         self.stb = Signal(reset_less=True)
1217         self.ack = Signal(reset=0, reset_less=True)
1218         self.out_norm = Signal(reset_less=True)
1219         self.in_accept = Signal(reset_less=True)
1220         self.temp_z = FPNumBase(width)
1221         self.temp_of = Overflow()
1222         self.out_z = FPNumBase(width)
1223         self.out_roundz = Signal(reset_less=True)
1224
1225     def setup(self, m, in_z, in_of, norm_stb, in_mid):
1226         """ links module to inputs and outputs
1227         """
1228         self.mod.setup(m, in_z, in_of, norm_stb,
1229                        self.in_accept, self.temp_z, self.temp_of,
1230                        self.out_z, self.out_norm)
1231
1232         m.d.comb += self.stb.eq(norm_stb)
1233         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1234
1235         if self.in_mid is not None:
1236             m.d.comb += self.in_mid.eq(in_mid)
1237
1238     def action(self, m):
1239         self.idsync(m)
1240         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1241         m.d.sync += self.temp_of.eq(self.mod.out_of)
1242         m.d.sync += self.temp_z.eq(self.out_z)
1243         with m.If(self.out_norm):
1244             with m.If(self.in_accept):
1245                 m.d.sync += [
1246                     self.ack.eq(1),
1247                 ]
1248             with m.Else():
1249                 m.d.sync += self.ack.eq(0)
1250         with m.Else():
1251             # normalisation not required (or done).
1252             m.next = "round"
1253             m.d.sync += self.ack.eq(1)
1254             m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1255
1256
1257 class FPNormToPack(FPState, FPID):
1258
1259     def __init__(self, width, id_wid):
1260         FPID.__init__(self, id_wid)
1261         FPState.__init__(self, "normalise_1")
1262         self.width = width
1263
1264     def setup(self, m, i, in_mid):
1265         """ links module to inputs and outputs
1266         """
1267
1268         # Normalisation (chained to input in_z+in_of)
1269         nmod = FPNorm1ModSingle(self.width, self.id_wid)
1270         n_out = nmod.ospec()
1271         nmod.setup(m, i, n_out.z)
1272         m.d.comb += n_out.roundz.eq(nmod.o.roundz)
1273
1274         # Rounding (chained to normalisation)
1275         rmod = FPRoundMod(self.width, self.id_wid)
1276         r_out_z = rmod.ospec()
1277         rmod.setup(m, n_out.z, n_out.roundz)
1278         m.d.comb += r_out_z.eq(rmod.out_z)
1279
1280         # Corrections (chained to rounding)
1281         cmod = FPCorrectionsMod(self.width, self.id_wid)
1282         c_out_z = cmod.ospec()
1283         cmod.setup(m, r_out_z)
1284         m.d.comb += c_out_z.eq(cmod.out_z)
1285
1286         # Pack (chained to corrections)
1287         self.pmod = FPPackMod(self.width, self.id_wid)
1288         self.out_z = self.pmod.ospec()
1289         self.pmod.setup(m, c_out_z)
1290
1291         # Multiplex ID
1292         if self.in_mid is not None:
1293             m.d.comb += self.in_mid.eq(in_mid)
1294
1295     def action(self, m):
1296         self.idsync(m) # copies incoming ID to outgoing
1297         m.d.sync += self.out_z.z.v.eq(self.pmod.o.z.v) # outputs packed result
1298         m.next = "pack_put_z"
1299
1300
1301 class FPRoundData:
1302
1303     def __init__(self, width, id_wid):
1304         self.z = FPNumBase(width, False)
1305         self.mid = Signal(id_wid, reset_less=True)
1306
1307     def eq(self, i):
1308         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1309
1310
1311 class FPRoundMod:
1312
1313     def __init__(self, width, id_wid):
1314         self.width = width
1315         self.id_wid = id_wid
1316         self.i = self.ispec()
1317         self.out_z = self.ospec()
1318
1319     def ispec(self):
1320         return FPNorm1Data(self.width, self.id_wid)
1321
1322     def ospec(self):
1323         return FPRoundData(self.width, self.id_wid)
1324
1325     def setup(self, m, in_z, roundz):
1326         m.submodules.roundz = self
1327
1328         m.d.comb += self.i.z.eq(in_z)
1329         m.d.comb += self.i.roundz.eq(roundz)
1330
1331     def elaborate(self, platform):
1332         m = Module()
1333         m.d.comb += self.out_z.eq(self.i)
1334         with m.If(self.i.roundz):
1335             m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa rounds up
1336             with m.If(self.i.z.m == self.i.z.m1s): # all 1s
1337                 m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1) # exponent up
1338         return m
1339
1340
1341 class FPRound(FPState, FPID):
1342
1343     def __init__(self, width, id_wid):
1344         FPState.__init__(self, "round")
1345         FPID.__init__(self, id_wid)
1346         self.mod = FPRoundMod(width)
1347         self.out_z = self.mod.ospec()
1348
1349     def setup(self, m, in_z, roundz, in_mid):
1350         """ links module to inputs and outputs
1351         """
1352         self.mod.setup(m, in_z, roundz)
1353
1354         if self.in_mid is not None:
1355             m.d.comb += self.in_mid.eq(in_mid)
1356
1357     def action(self, m):
1358         self.idsync(m)
1359         m.d.sync += self.out_z.eq(self.mod.out_z)
1360         m.next = "corrections"
1361
1362
1363 class FPCorrectionsMod:
1364
1365     def __init__(self, width, id_wid):
1366         self.width = width
1367         self.id_wid = id_wid
1368         self.in_z = self.ispec()
1369         self.out_z = self.ospec()
1370
1371     def ispec(self):
1372         return FPRoundData(self.width, self.id_wid)
1373
1374     def ospec(self):
1375         return FPRoundData(self.width, self.id_wid)
1376
1377     def setup(self, m, in_z):
1378         """ links module to inputs and outputs
1379         """
1380         m.submodules.corrections = self
1381         m.d.comb += self.in_z.eq(in_z)
1382
1383     def elaborate(self, platform):
1384         m = Module()
1385         m.submodules.corr_in_z = self.in_z.z
1386         m.submodules.corr_out_z = self.out_z.z
1387         m.d.comb += self.out_z.eq(self.in_z)
1388         with m.If(self.in_z.z.is_denormalised):
1389             m.d.comb += self.out_z.z.e.eq(self.in_z.z.N127)
1390         return m
1391
1392
1393 class FPCorrections(FPState, FPID):
1394
1395     def __init__(self, width, id_wid):
1396         FPState.__init__(self, "corrections")
1397         FPID.__init__(self, id_wid)
1398         self.mod = FPCorrectionsMod(width)
1399         self.out_z = self.mod.ospec()
1400
1401     def setup(self, m, in_z, in_mid):
1402         """ links module to inputs and outputs
1403         """
1404         self.mod.setup(m, in_z)
1405         if self.in_mid is not None:
1406             m.d.comb += self.in_mid.eq(in_mid)
1407
1408     def action(self, m):
1409         self.idsync(m)
1410         m.d.sync += self.out_z.eq(self.mod.out_z)
1411         m.next = "pack"
1412
1413
1414 class FPPackData:
1415
1416     def __init__(self, width, id_wid):
1417         self.z = FPNumOut(width, False)
1418         self.mid = Signal(id_wid, reset_less=True)
1419
1420     def eq(self, i):
1421         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1422
1423
1424 class FPPackMod:
1425
1426     def __init__(self, width, id_wid):
1427         self.width = width
1428         self.id_wid = id_wid
1429         self.i = self.ispec()
1430         self.o = self.ospec()
1431
1432     def ispec(self):
1433         return FPRoundData(self.width, self.id_wid)
1434
1435     def ospec(self):
1436         return FPPackData(self.width, self.id_wid)
1437
1438     def setup(self, m, in_z):
1439         """ links module to inputs and outputs
1440         """
1441         m.submodules.pack = self
1442         m.d.comb += self.i.eq(in_z)
1443
1444     def elaborate(self, platform):
1445         m = Module()
1446         m.submodules.pack_in_z = self.i.z
1447         with m.If(self.i.z.is_overflowed):
1448             m.d.comb += self.o.z.inf(self.i.z.s)
1449         with m.Else():
1450             m.d.comb += self.o.z.create(self.i.z.s, self.i.z.e, self.i.z.m)
1451         return m
1452
1453
1454 class FPPackData:
1455     def __init__(self, width, id_wid):
1456         self.z = FPNumOut(width, False)
1457         self.mid = Signal(id_wid, reset_less=True)
1458
1459     def eq(self, i):
1460         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1461
1462
1463 class FPPack(FPState, FPID):
1464
1465     def __init__(self, width, id_wid):
1466         FPState.__init__(self, "pack")
1467         FPID.__init__(self, id_wid)
1468         self.mod = FPPackMod(width)
1469         self.out_z = self.ospec()
1470
1471     def ispec(self):
1472         return self.mod.ispec()
1473
1474     def ospec(self):
1475         return self.mod.ospec()
1476
1477     def setup(self, m, in_z, in_mid):
1478         """ links module to inputs and outputs
1479         """
1480         self.mod.setup(m, in_z)
1481         if self.in_mid is not None:
1482             m.d.comb += self.in_mid.eq(in_mid)
1483
1484     def action(self, m):
1485         self.idsync(m)
1486         m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1487         m.next = "pack_put_z"
1488
1489
1490 class FPPutZ(FPState):
1491
1492     def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1493         FPState.__init__(self, state)
1494         if to_state is None:
1495             to_state = "get_ops"
1496         self.to_state = to_state
1497         self.in_z = in_z
1498         self.out_z = out_z
1499         self.in_mid = in_mid
1500         self.out_mid = out_mid
1501
1502     def action(self, m):
1503         if self.in_mid is not None:
1504             m.d.sync += self.out_mid.eq(self.in_mid)
1505         m.d.sync += [
1506           self.out_z.v.eq(self.in_z.v)
1507         ]
1508         with m.If(self.out_z.stb & self.out_z.ack):
1509             m.d.sync += self.out_z.stb.eq(0)
1510             m.next = self.to_state
1511         with m.Else():
1512             m.d.sync += self.out_z.stb.eq(1)
1513
1514
1515 class FPPutZIdx(FPState):
1516
1517     def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1518         FPState.__init__(self, state)
1519         if to_state is None:
1520             to_state = "get_ops"
1521         self.to_state = to_state
1522         self.in_z = in_z
1523         self.out_zs = out_zs
1524         self.in_mid = in_mid
1525
1526     def action(self, m):
1527         outz_stb = Signal(reset_less=True)
1528         outz_ack = Signal(reset_less=True)
1529         m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1530                      outz_ack.eq(self.out_zs[self.in_mid].ack),
1531                     ]
1532         m.d.sync += [
1533           self.out_zs[self.in_mid].v.eq(self.in_z.v)
1534         ]
1535         with m.If(outz_stb & outz_ack):
1536             m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1537             m.next = self.to_state
1538         with m.Else():
1539             m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1540
1541 class FPADDBaseData:
1542
1543     def __init__(self, width, id_wid):
1544         self.width = width
1545         self.id_wid = id_wid
1546         self.a  = Signal(width)
1547         self.b  = Signal(width)
1548         self.mid = Signal(id_wid, reset_less=True)
1549
1550     def eq(self, i):
1551         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
1552
1553
1554 class FPADDBaseMod(FPID):
1555
1556     def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1557         """ IEEE754 FP Add
1558
1559             * width: bit-width of IEEE754.  supported: 16, 32, 64
1560             * id_wid: an identifier that is sync-connected to the input
1561             * single_cycle: True indicates each stage to complete in 1 clock
1562             * compact: True indicates a reduced number of stages
1563         """
1564         FPID.__init__(self, id_wid)
1565         self.width = width
1566         self.id_wid = id_wid
1567         self.single_cycle = single_cycle
1568         self.compact = compact
1569
1570         self.in_t = Trigger()
1571         self.i = self.ispec()
1572         self.out_z = FPOp(width)
1573
1574         self.states = []
1575
1576     def ispec(self):
1577         return FPADDBaseData(self.width, self.id_wid)
1578
1579     def add_state(self, state):
1580         self.states.append(state)
1581         return state
1582
1583     def get_fragment(self, platform=None):
1584         """ creates the HDL code-fragment for FPAdd
1585         """
1586         m = Module()
1587         m.submodules.out_z = self.out_z
1588         m.submodules.in_t = self.in_t
1589         if self.compact:
1590             self.get_compact_fragment(m, platform)
1591         else:
1592             self.get_longer_fragment(m, platform)
1593
1594         with m.FSM() as fsm:
1595
1596             for state in self.states:
1597                 with m.State(state.state_from):
1598                     state.action(m)
1599
1600         return m
1601
1602     def get_longer_fragment(self, m, platform=None):
1603
1604         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1605                                       self.in_a, self.in_b, self.width))
1606         get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1607         a = get.out_op1
1608         b = get.out_op2
1609
1610         sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1611         sc.setup(m, a, b, self.in_mid)
1612
1613         dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1614         dn.setup(m, a, b, sc.in_mid)
1615
1616         if self.single_cycle:
1617             alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1618             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1619         else:
1620             alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1621             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1622
1623         add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1624         add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1625
1626         add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1627         add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1628
1629         if self.single_cycle:
1630             n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1631             n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1632         else:
1633             n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1634             n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1635
1636         rn = self.add_state(FPRound(self.width, self.id_wid))
1637         rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1638
1639         cor = self.add_state(FPCorrections(self.width, self.id_wid))
1640         cor.setup(m, rn.out_z, rn.in_mid)
1641
1642         pa = self.add_state(FPPack(self.width, self.id_wid))
1643         pa.setup(m, cor.out_z, rn.in_mid)
1644
1645         ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1646                                     pa.in_mid, self.out_mid))
1647
1648         pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1649                                     pa.in_mid, self.out_mid))
1650
1651     def get_compact_fragment(self, m, platform=None):
1652
1653         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1654                                       self.i.a, self.i.b,
1655                                       self.width, self.id_wid))
1656         get.setup(m, self.i, self.in_t.stb, self.in_t.ack)
1657         a = get.o.a
1658         b = get.o.b
1659
1660         sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1661         sc.setup(m, get.o, self.in_mid)
1662
1663         alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1664         alm.setup(m, sc.o, sc.in_mid)
1665
1666         n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1667         n1.setup(m, alm.a1o, alm.in_mid)
1668
1669         ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z.z, self.out_z,
1670                                     n1.in_mid, self.out_mid))
1671
1672         pz = self.add_state(FPPutZ("put_z", sc.out_z.z, self.out_z,
1673                                     sc.in_mid, self.out_mid))
1674
1675
1676 class FPADDBase(FPState, FPID):
1677
1678     def __init__(self, width, id_wid=None, single_cycle=False):
1679         """ IEEE754 FP Add
1680
1681             * width: bit-width of IEEE754.  supported: 16, 32, 64
1682             * id_wid: an identifier that is sync-connected to the input
1683             * single_cycle: True indicates each stage to complete in 1 clock
1684         """
1685         FPID.__init__(self, id_wid)
1686         FPState.__init__(self, "fpadd")
1687         self.width = width
1688         self.single_cycle = single_cycle
1689         self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1690
1691         self.in_t = Trigger()
1692         self.in_a  = Signal(width)
1693         self.in_b  = Signal(width)
1694         #self.out_z = FPOp(width)
1695
1696         self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1697         self.in_accept = Signal(reset_less=True)
1698         self.add_stb = Signal(reset_less=True)
1699         self.add_ack = Signal(reset=0, reset_less=True)
1700
1701     def setup(self, m, a, b, add_stb, in_mid, out_z, out_mid):
1702         self.out_z = out_z
1703         self.out_mid = out_mid
1704         m.d.comb += [self.in_a.eq(a),
1705                      self.in_b.eq(b),
1706                      self.mod.i.a.eq(self.in_a),
1707                      self.mod.i.b.eq(self.in_b),
1708                      self.in_mid.eq(in_mid),
1709                      self.mod.in_mid.eq(self.in_mid),
1710                      self.z_done.eq(self.mod.out_z.trigger),
1711                      #self.add_stb.eq(add_stb),
1712                      self.mod.in_t.stb.eq(self.in_t.stb),
1713                      self.in_t.ack.eq(self.mod.in_t.ack),
1714                      self.out_mid.eq(self.mod.out_mid),
1715                      self.out_z.v.eq(self.mod.out_z.v),
1716                      self.out_z.stb.eq(self.mod.out_z.stb),
1717                      self.mod.out_z.ack.eq(self.out_z.ack),
1718                     ]
1719
1720         m.d.sync += self.add_stb.eq(add_stb)
1721         m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1722         m.d.sync += self.out_z.ack.eq(0) # likewise
1723         #m.d.sync += self.in_t.stb.eq(0)
1724
1725         m.submodules.fpadd = self.mod
1726
1727     def action(self, m):
1728
1729         # in_accept is set on incoming strobe HIGH and ack LOW.
1730         m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1731
1732         #with m.If(self.in_t.ack):
1733         #    m.d.sync += self.in_t.stb.eq(0)
1734         with m.If(~self.z_done):
1735             # not done: test for accepting an incoming operand pair
1736             with m.If(self.in_accept):
1737                 m.d.sync += [
1738                     self.add_ack.eq(1), # acknowledge receipt...
1739                     self.in_t.stb.eq(1), # initiate add
1740                 ]
1741             with m.Else():
1742                 m.d.sync += [self.add_ack.eq(0),
1743                              self.in_t.stb.eq(0),
1744                              self.out_z.ack.eq(1),
1745                             ]
1746         with m.Else():
1747             # done: acknowledge, and write out id and value
1748             m.d.sync += [self.add_ack.eq(1),
1749                          self.in_t.stb.eq(0)
1750                         ]
1751             m.next = "put_z"
1752
1753             return
1754
1755             if self.in_mid is not None:
1756                 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1757
1758             m.d.sync += [
1759               self.out_z.v.eq(self.mod.out_z.v)
1760             ]
1761             # move to output state on detecting z ack
1762             with m.If(self.out_z.trigger):
1763                 m.d.sync += self.out_z.stb.eq(0)
1764                 m.next = "put_z"
1765             with m.Else():
1766                 m.d.sync += self.out_z.stb.eq(1)
1767
1768 class ResArray:
1769     def __init__(self, width, id_wid):
1770         self.width = width
1771         self.id_wid = id_wid
1772         res = []
1773         for i in range(rs_sz):
1774             out_z = FPOp(width)
1775             out_z.name = "out_z_%d" % i
1776             res.append(out_z)
1777         self.res = Array(res)
1778         self.in_z = FPOp(width)
1779         self.in_mid = Signal(self.id_wid, reset_less=True)
1780
1781     def setup(self, m, in_z, in_mid):
1782         m.d.comb += [self.in_z.eq(in_z),
1783                      self.in_mid.eq(in_mid)]
1784
1785     def get_fragment(self, platform=None):
1786         """ creates the HDL code-fragment for FPAdd
1787         """
1788         m = Module()
1789         m.submodules.res_in_z = self.in_z
1790         m.submodules += self.res
1791
1792         return m
1793
1794     def ports(self):
1795         res = []
1796         for z in self.res:
1797             res += z.ports()
1798         return res
1799
1800
1801 class FPADD(FPID):
1802     """ FPADD: stages as follows:
1803
1804         FPGetOp (a)
1805            |
1806         FPGetOp (b)
1807            |
1808         FPAddBase---> FPAddBaseMod
1809            |            |
1810         PutZ          GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1811
1812         FPAddBase is tricky: it is both a stage and *has* stages.
1813         Connection to FPAddBaseMod therefore requires an in stb/ack
1814         and an out stb/ack.  Just as with Add1-Norm1 interaction, FPGetOp
1815         needs to be the thing that raises the incoming stb.
1816     """
1817
1818     def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1819         """ IEEE754 FP Add
1820
1821             * width: bit-width of IEEE754.  supported: 16, 32, 64
1822             * id_wid: an identifier that is sync-connected to the input
1823             * single_cycle: True indicates each stage to complete in 1 clock
1824         """
1825         self.width = width
1826         self.id_wid = id_wid
1827         self.single_cycle = single_cycle
1828
1829         #self.out_z = FPOp(width)
1830         self.ids = FPID(id_wid)
1831
1832         rs = []
1833         for i in range(rs_sz):
1834             in_a  = FPOp(width)
1835             in_b  = FPOp(width)
1836             in_a.name = "in_a_%d" % i
1837             in_b.name = "in_b_%d" % i
1838             rs.append((in_a, in_b))
1839         self.rs = Array(rs)
1840
1841         res = []
1842         for i in range(rs_sz):
1843             out_z = FPOp(width)
1844             out_z.name = "out_z_%d" % i
1845             res.append(out_z)
1846         self.res = Array(res)
1847
1848         self.states = []
1849
1850     def add_state(self, state):
1851         self.states.append(state)
1852         return state
1853
1854     def get_fragment(self, platform=None):
1855         """ creates the HDL code-fragment for FPAdd
1856         """
1857         m = Module()
1858         m.submodules += self.rs
1859
1860         in_a = self.rs[0][0]
1861         in_b = self.rs[0][1]
1862
1863         out_z = FPOp(self.width)
1864         out_mid = Signal(self.id_wid, reset_less=True)
1865         m.submodules.out_z = out_z
1866
1867         geta = self.add_state(FPGetOp("get_a", "get_b",
1868                                       in_a, self.width))
1869         geta.setup(m, in_a)
1870         a = geta.out_op
1871
1872         getb = self.add_state(FPGetOp("get_b", "fpadd",
1873                                       in_b, self.width))
1874         getb.setup(m, in_b)
1875         b = getb.out_op
1876
1877         ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1878         ab = self.add_state(ab)
1879         ab.setup(m, a, b, getb.out_decode, self.ids.in_mid,
1880                  out_z, out_mid)
1881
1882         pz = self.add_state(FPPutZIdx("put_z", ab.out_z, self.res,
1883                                     out_mid, "get_a"))
1884
1885         with m.FSM() as fsm:
1886
1887             for state in self.states:
1888                 with m.State(state.state_from):
1889                     state.action(m)
1890
1891         return m
1892
1893
1894 if __name__ == "__main__":
1895     if True:
1896         alu = FPADD(width=32, id_wid=5, single_cycle=True)
1897         main(alu, ports=alu.rs[0][0].ports() + \
1898                         alu.rs[0][1].ports() + \
1899                         alu.res[0].ports() + \
1900                         [alu.ids.in_mid, alu.ids.out_mid])
1901     else:
1902         alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1903         main(alu, ports=[alu.in_a, alu.in_b] + \
1904                         alu.in_t.ports() + \
1905                         alu.out_z.ports() + \
1906                         [alu.in_mid, alu.out_mid])
1907
1908
1909     # works... but don't use, just do "python fname.py convert -t v"
1910     #print (verilog.convert(alu, ports=[
1911     #                        ports=alu.in_a.ports() + \
1912     #                              alu.in_b.ports() + \
1913     #                              alu.out_z.ports())