1 from nmigen
import Module
, Signal
2 from nmigen
.compat
.sim
import run_simulation
4 from nmigen_add_experiment
import FPADD
12 def get_fragment(self
, platform
=None):
15 m
.d
.comb
+= self
.x
.eq(self
.a | self
.b
)
19 def check_case(dut
, a
, b
, x
):
21 yield dut
.in_a_stb
.eq(1)
24 a_ack
= (yield dut
.in_a_ack
)
27 yield dut
.in_b_stb
.eq(1)
28 b_ack
= (yield dut
.in_b_ack
)
33 out_z_stb
= (yield dut
.out_z_stb
)
36 yield dut
.in_a_stb
.eq(0)
37 yield dut
.in_b_stb
.eq(0)
38 yield dut
.out_z_ack
.eq(1)
40 yield dut
.out_z_ack
.eq(0)
46 yield from check_case(dut
, 0, 0, 0)
47 yield from check_case(dut
, 0x3F800000, 0x40000000, 0x40400000)
48 #yield from check_case(dut, 1, 0, 1)
49 #yield from check_case(dut, 1, 1, 1)
51 if __name__
== '__main__':
53 run_simulation(dut
, testbench(dut
), vcd_name
="test_add.vcd")