src/add/test_dual.py

   1 from sfpy import Float32
   2 from nmigen.compat.sim import run_simulation
   3 from dual_add_experiment import ALU
   4
   5
   6 def get_case(dut, a, b, c):
   7     yield dut.c.v.eq(c)
   8     yield dut.c.stb.eq(1)
   9     yield
  10     yield
  11     c_ack = (yield dut.c.ack)
  12     assert c_ack == 0
  13
  14     yield dut.a.v.eq(a)
  15     yield dut.a.stb.eq(1)
  16     yield
  17     yield
  18     a_ack = (yield dut.a.ack)
  19     assert a_ack == 0
  20
  21     yield dut.b.v.eq(b)
  22     yield dut.b.stb.eq(1)
  23     yield
  24     yield
  25     b_ack = (yield dut.b.ack)
  26     assert b_ack == 0
  27
  28     while True:
  29         yield
  30         out_z_stb = (yield dut.z.stb)
  31         if not out_z_stb:
  32             continue
  33
  34         out_z = yield dut.z.v
  35
  36         yield dut.a.stb.eq(0)
  37         yield dut.b.stb.eq(0)
  38         yield dut.c.stb.eq(0)
  39         yield dut.z.ack.eq(1)
  40         yield
  41         yield dut.z.ack.eq(0)
  42         yield
  43         yield
  44         break
  45
  46     return out_z
  47
  48 def check_case(dut, a, b, c, z):
  49     out_z = yield from get_case(dut, a, b, c)
  50     assert out_z == z, "Output z 0x%x not equal to expected 0x%x" % (out_z, z)
  51
  52 def testbench(dut):
  53     yield from check_case(dut, 0, 0, 0, 0)
  54     yield from check_case(dut, 0x3F800000, 0x40000000, 0xc0000000, 0x3F800000)
  55
  56 if __name__ == '__main__':
  57     dut = ALU(width=32)
  58     run_simulation(dut, testbench(dut), vcd_name="test_dual_add.vcd")
  59