src/bsv/bsv_lib/slow_peripherals_template.bsv

   1 package slow_peripherals;
   2         /*===== Project imports =====*/
   3         import defined_types::*;
   4         import AXI4_Lite_Fabric::*;
   5         import AXI4_Lite_Types::*;
   6         import AXI4_Fabric::*;
   7         import AXI4_Types::*;
   8         import Semi_FIFOF::*;
   9         import AXI4Lite_AXI4_Bridge::*;
  10         import slow_memory_map::*;
  11         `include "instance_defines.bsv"
  12     /* ==== define the number of slow peripheral irqs ==== */
  13 {11}
  14         /*===========================*/
  15         /*=== package imports ===*/
  16         import Clocks::*;
  17         import GetPut::*;
  18         import ClientServer::*;
  19         import Connectable::*;
  20         import Vector::*;
  21         import FIFO::*;
  22         /*=======================*/
  23         /*===== Import the slow peripherals ====*/
  24 {0}
  25     `ifdef CLINT
  26         import clint::*;
  27     `endif
  28     `ifdef PLIC
  29         import plic             ::*;
  30     `endif
  31         `ifdef AXIEXP
  32                 import axiexpansion     ::*;
  33         `endif
  34         /*=====================================*/
  35
  36         /*===== interface declaration =====*/
  37         interface SP_dedicated_ios;
  38                 `ifdef AXIEXP
  39                         interface Get#(Bit#(67)) axiexp1_out;
  40                         interface Put#(Bit#(67)) axiexp1_in;
  41                 `endif
  42         endinterface
  43         interface Ifc_slow_peripherals;
  44                 interface AXI4_Slave_IFC#(`PADDR,`DATA,`USERSPACE) axi_slave;
  45                 interface SP_dedicated_ios slow_ios;
  46                 `ifdef CLINT
  47                         method Bit#(1) msip_int;
  48                         method Bit#(1) mtip_int;
  49                         method Bit#(`DATA) mtime;
  50                 `endif
  51                 `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note;
  52         `endif
  53         interface IOCellSide iocell_side; // mandatory interface
  54         `ifdef PLIC
  55 {1}
  56         `endif
  57         endinterface
  58         /*================================*/
  59
  60         (*synthesize*)
  61         module mkslow_peripherals#(Clock fast_clock, Reset fast_reset,
  62                                Clock uart_clock, Reset uart_reset
  63                               `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif
  64                               )(Ifc_slow_peripherals);
  65                 Clock sp_clock <-exposeCurrentClock; // slow peripheral clock
  66                 Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
  67
  68                 /*======= Module declarations for each peripheral =======*/
  69 {5}
  70                 `ifdef CLINT
  71                         Ifc_clint       clint <- mkclint();
  72                 `endif
  73                 `ifdef PLIC
  74                         Ifc_PLIC_AXI    plic <- mkplicperipheral();
  75             Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
  76             Vector#(`INTERRUPT_PINS, FIFO#(bit))
  77                             ff_gateway_queue <- replicateM(mkFIFO);
  78                 `endif
  79                 `ifdef AXIEXP
  80                         Ifc_AxiExpansion axiexp1 <- mkAxiExpansion();
  81                 `endif
  82         Ifc_pinmux pinmux <- mkpinmux; // mandatory
  83
  84                 /*=======================================================*/
  85
  86             AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `PADDR, `DATA,`USERSPACE)
  87                 slow_fabric <- mkAXI4_Lite_Fabric(fn_slow_address_mapping);
  88                 Ifc_AXI4Lite_AXI4_Bridge
  89                 bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
  90
  91                 mkConnection (bridge.axi4_lite_master, slow_fabric.v_from_masters [0]);
  92                 /*======= Slave connections to AXI4Lite fabric =========*/
  93 {6}
  94                 `ifdef CLINT
  95                         mkConnection (slow_fabric.v_to_slaves
  96                     [fromInteger(valueOf(CLINT_slave_num))],
  97                     clint.axi4_slave);
  98                 `endif
  99                 `ifdef PLIC
 100                         mkConnection (slow_fabric.v_to_slaves
 101                     [fromInteger(valueOf(Plic_slave_num))],
 102                     plic.axi4_slave_plic); //
 103                 `endif
 104                 `ifdef AXIEXP
 105                 mkConnection (slow_fabric.v_to_slaves
 106                     [fromInteger(valueOf(AxiExp1_slave_num))],
 107                     axiexp1.axi_slave); //
 108                 `endif
 109
 110     /*========== pinmux connections ============*/
 111 {7}
 112 {8}
 113
 114     /*=================== PLIC Connections ==================== */
 115 `ifdef PLIC
 116 {10}
 117
 118     rule rl_completion_msg_from_plic;
 119           let id <- plic.intrpt_completion;
 120       interrupt_id <= id;
 121       `ifdef verbose
 122         $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id);
 123        `endif
 124         endrule
 125
 126     for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
 127             rule deq_gateway_queue;
 128                     if(interrupt_id==fromInteger(i)) begin
 129                             ff_gateway_queue[i].deq;
 130           `ifdef verbose
 131             $display($time,"Dequeing the Interrupt request for ID: %d",i);
 132           `endif
 133         end
 134       endrule
 135     end
 136     /*TODO DMA interrupt need to be connected to the plic */
 137     for(Integer i=1; i<8; i=i+1) begin
 138       rule rl_connect_dma_interrupts_to_plic;
 139        `ifdef DMA
 140             if(dma.interrupt_to_processor[i-1]==1'b1) begin
 141                 ff_gateway_queue[i].enq(1);
 142                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 143             end
 144         `else
 145             ff_gateway_queue[i].enq(0);
 146         `endif
 147       endrule
 148     end
 149
 150 `endif // end PLIC
 151         /*======================================================= */
 152
 153                 /* ===== interface definition =======*/
 154                 interface axi_slave=bridge.axi_slave;
 155                 `ifdef PLIC method intrpt_note = plic.intrpt_note; `endif
 156                 `ifdef CLINT
 157                         method msip_int=clint.msip_int;
 158                         method mtip_int=clint.mtip_int;
 159                         method mtime=clint.mtime;
 160                 `endif
 161 `ifdef PLIC
 162 {12}
 163 `endif // end PLIC
 164                 interface SP_dedicated_ios slow_ios;
 165         /* template for dedicated peripherals
 166                         `ifdef UART0
 167                                 interface uart0_coe=uart0.coe_rs232;
 168                         `endif
 169                         `ifdef UART1
 170                                 interface uart1_coe=uart1.coe_rs232;
 171                         `endif
 172                         `ifdef I2C0
 173                                 interface i2c0_out=i2c0.out;
 174                         `endif
 175                         `ifdef I2C1
 176                                 interface i2c1_out=i2c1.out;
 177                         `endif
 178                         `ifdef QSPI0
 179                                 interface qspi0_out = qspi0.out;
 180                         `endif
 181                         `ifdef QSPI1
 182                                 interface qspi1_out = qspi1.out;
 183                         `endif
 184                         `ifdef AXIEXP
 185                                 interface axiexp1_out=axiexp1.slave_out;
 186                                 interface axiexp1_in=axiexp1.slave_in;
 187                         `endif
 188             `ifdef PWM_AXI4Lite
 189                 interface pwm_o = pwm_bus.pwm_io;
 190             `endif
 191        */
 192                 endinterface
 193         interface iocell_side=pinmux.iocell_side;
 194 {9}
 195 {13}
 196                 /*===================================*/
 197         endmodule
 198 endpackage