fix PADDR to 32
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 28 Jul 2018 09:16:14 +0000 (10:16 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 28 Jul 2018 09:16:14 +0000 (10:16 +0100)
src/bsv/bsv_lib/slow_peripherals_template.bsv
src/bsv/bsv_lib/slow_tuple2_template.bsv
src/bsv/bsv_lib/soc_template.bsv
src/bsv/peripheral_gen/flexbus.py
src/bsv/pinmux_generator.py

index 2f4a828186a1b4644dccb2767eae81a3fb0e074d..9c992feea851f8fa1910e61bccafe9477babbff6 100644 (file)
@@ -41,7 +41,7 @@ package slow_peripherals;
                `endif
        endinterface
        interface Ifc_slow_peripherals;
-               interface AXI4_Slave_IFC#(`ADDR,`DATA,`USERSPACE) axi_slave;
+               interface AXI4_Slave_IFC#(`PADDR,`DATA,`USERSPACE) axi_slave;
                interface SP_dedicated_ios slow_ios;
                `ifdef CLINT
                        method Bit#(1) msip_int;
@@ -83,7 +83,7 @@ package slow_peripherals;
 
                /*=======================================================*/
 
-           AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `ADDR, `DATA,`USERSPACE)
+           AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `PADDR, `DATA,`USERSPACE)
                 slow_fabric <- mkAXI4_Lite_Fabric(fn_slow_address_mapping);
                Ifc_AXI4Lite_AXI4_Bridge
                 bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
index ce5989b27aaa22eec41182d790c509feb5d2d88f..dbde384b89835149097106b6da691f35a2e4d5c4 100644 (file)
@@ -11,7 +11,7 @@ package slow_memory_map;
     /* ==== define the number of slow peripheral irqs ==== */
 
        function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves)))
-                     fn_slow_address_mapping (Bit#(`ADDR) addr);
+                     fn_slow_address_mapping (Bit#(`PADDR) addr);
         `ifdef CLINT
             if(addr>=`ClintBase && addr<=`ClintEnd)
                 return tuple2(True,fromInteger(valueOf(CLINT_slave_num)));
index 166ba811c7e1bcdb2aadee6a16cb850352308283..65e1dce0d9a717c2d5b580fbd22f610e5ba9c3f5 100644 (file)
@@ -96,7 +96,7 @@ package socgen;
         `endif
         `ifdef DDR
             (*prefix="M_AXI"*) interface
-                   AXI4_Master_IFC#(`ADDR, `DATA, `USERSPACE) master;
+                   AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
         `endif
         `ifdef HYPER
              (*always_ready,always_enabled*)   
@@ -152,7 +152,7 @@ package socgen;
 
         // Fabric
         AXI4_Fabric_IFC #(Num_Masters, Num_Fast_Slaves,
-                          `ADDR, `DATA,`USERSPACE)
+                          `PADDR, `DATA,`USERSPACE)
                         fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 
         // Connect traffic generators to fabric
index 7302d469f2e0ed65fa4d65e3ccd3b2266c0e5da9..074e84366c05d9150922a350f522564c1941d61e 100644 (file)
@@ -18,7 +18,7 @@ class flexbus(PBase):
 
     def mkfast_peripheral(self):
         return "AXI4_Slave_to_FlexBus_Master_Xactor_IFC " + \
-               "#(`ADDR, `DATA, `USERSPACE)\n" + \
+               "#(`PADDR, `DATA, `USERSPACE)\n" + \
                "        fb{0} <- mkAXI4_Slave_to_FlexBus_Master_Xactor;"
 
     def _mk_connection(self, name=None, count=0):
index 1589468ab324bc463022e667cfd2745c60c8235c..36d6e4eef3ebbf18e9cbff5958e857bf945284cd 100644 (file)
@@ -443,7 +443,7 @@ def write_instances(idef, p, ifaces):
     with open(idef, 'w') as bsv_file:
         txt = '''\
 `define ADDR {0}
-`define PADDR {0}
+`define PADDR 32
 `define DATA {1}
 `define Reg_width {1}
 `define USERSPACE 0