src/bsv/peripheral_gen.py

   1 import types
   2 from copy import deepcopy
   3
   4
   5 class PBase(object):
   6     def __init__(self, name):
   7         self.name = name
   8
   9     def slowifdeclmux(self):
  10         return ''
  11
  12     def slowifdecl(self):
  13         return ''
  14
  15     def axibase(self, name, ifacenum):
  16         name = name.upper()
  17         return "%(name)s%(ifacenum)dBase" % locals()
  18
  19     def axiend(self, name, ifacenum):
  20         name = name.upper()
  21         return "%(name)s%(ifacenum)dEnd" % locals()
  22
  23     def axi_reg_def(self, start, name, ifacenum):
  24         name = name.upper()
  25         offs = self.num_axi_regs32() * 4 * 16
  26         end = start + offs - 1
  27         bname = self.axibase(name, ifacenum)
  28         bend = self.axiend(name, ifacenum)
  29         comment = "%d 32-bit regs" % self.num_axi_regs32()
  30         return ("    `define %(bname)s 'h%(start)08X\n"
  31                 "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
  32                 offs)
  33
  34     def axi_slave_name(self, name, ifacenum):
  35         name = name.upper()
  36         return "{0}{1}_slave_num".format(name, ifacenum)
  37
  38     def axi_slave_idx(self, idx, name, ifacenum):
  39         name = self.axi_slave_name(name, ifacenum)
  40         return ("typedef {0} {1};".format(idx, name), 1)
  41
  42     def axi_addr_map(self, name, ifacenum):
  43         bname = self.axibase(name, ifacenum)
  44         bend = self.axiend(name, ifacenum)
  45         name = self.axi_slave_name(name, ifacenum)
  46         return """\
  47         if(addr>=`{0} && addr<=`{1})
  48             return tuple2(True,fromInteger(valueOf({2})));
  49         else""".format(bname, bend, name)
  50
  51     def mk_pincon(self, name, count):
  52         # TODO: really should be using bsv.interface_decl.Interfaces
  53         # pin-naming rules.... logic here is hard-coded to duplicate
  54         # it (see Interface.__init__ outen)
  55         ret = []
  56         for p in self.peripheral.pinspecs:
  57             typ = p['type']
  58             pname = p['name']
  59             #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
  60             n = name  # "{0}{1}".format(self.name, self.mksuffix(name, count))
  61             ret.append("    //%s %s" % (n, str(p)))
  62             sname = self.peripheral.pname(pname).format(count)
  63             ps = "pinmux.peripheral_side.%s" % sname
  64             if typ == 'out' or typ == 'inout':
  65                 ret.append("    rule con_%s%d_%s_out;" % (name, count, pname))
  66                 fname = self.pinname_out(pname)
  67                 if fname:
  68                     if p.get('outen'):
  69                         ps_ = ps + '_out'
  70                     else:
  71                         ps_ = ps
  72                     if not n.startswith('gpio'): # XXX EURGH! horrible hack
  73                       n_ = "{0}{1}".format(n, count)
  74                     else:
  75                       n_ = n
  76                     ret.append("      {0}({1}.{2});".format(ps_, n_, fname))
  77                 fname = None
  78                 if p.get('outen'):
  79                     fname = self.pinname_outen(pname)
  80                 if fname:
  81                     if isinstance(fname, str):
  82                         fname = "{0}{1}.{2}".format(n, count, fname)
  83                     fname = self.pinname_tweak(pname, 'outen', fname)
  84                     ret.append("      {0}_outen({1});".format(ps, fname))
  85                 ret.append("    endrule")
  86             if typ == 'in' or typ == 'inout':
  87                 fname = self.pinname_in(pname)
  88                 if fname:
  89                     if p.get('outen'):
  90                         ps_ = ps + '_in'
  91                     else:
  92                         ps_ = ps
  93                     ret.append(
  94                         "    rule con_%s%d_%s_in;" %
  95                         (name, count, pname))
  96                     n_ = "{0}{1}".format(n, count)
  97                     ret.append("      {1}.{2}({0});".format(ps_, n_, fname))
  98                     ret.append("    endrule")
  99         return '\n'.join(ret)
 100
 101     def mk_cellconn(self, *args):
 102         return ''
 103
 104     def mkslow_peripheral(self, size=0):
 105         return ''
 106
 107     def mksuffix(self, name, i):
 108         return i
 109
 110     def __mk_connection(self, con, aname):
 111         txt = "        mkConnection (slow_fabric.v_to_slaves\n" + \
 112             "                    [fromInteger(valueOf({1}))],\n" + \
 113             "                    {0});"
 114
 115         print "PBase __mk_connection", self.name, aname
 116         if not con:
 117             return ''
 118         return txt.format(con, aname)
 119
 120     def mk_connection(self, count, name=None):
 121         if name is None:
 122             name = self.name
 123         print "PBase mk_conn", self.name, count
 124         aname = self.axi_slave_name(name, count)
 125         #dname = self.mksuffix(name, count)
 126         #dname = "{0}{1}".format(name, dname)
 127         con = self._mk_connection(name, count).format(count, aname)
 128         return self.__mk_connection(con, aname)
 129
 130     def _mk_connection(self, name=None, count=0):
 131         return ''
 132
 133     def pinname_out(self, pname):
 134         return ''
 135
 136     def pinname_in(self, pname):
 137         return ''
 138
 139     def pinname_outen(self, pname):
 140         return ''
 141
 142     def pinname_tweak(self, pname, typ, txt):
 143         return txt
 144
 145
 146 class uart(PBase):
 147
 148     def slowimport(self):
 149         return "          import Uart_bs         :: *;\n" + \
 150                "          import RS232_modified::*;"
 151
 152     def slowifdecl(self):
 153         return "            interface RS232 uart{0}_coe;\n" + \
 154                "            method Bit#(1) uart{0}_intr;"
 155
 156     def num_axi_regs32(self):
 157         return 8
 158
 159     def mkslow_peripheral(self, size=0):
 160         return "        Ifc_Uart_bs uart{0} <- \n" + \
 161                "                mkUart_bs(clocked_by sp_clock,\n" + \
 162                "                    reset_by uart_reset, sp_clock, sp_reset);"
 163
 164     def _mk_connection(self, name=None, count=0):
 165         return "uart{0}.slave_axi_uart"
 166
 167     def pinname_out(self, pname):
 168         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 169
 170     def pinname_in(self, pname):
 171         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 172
 173
 174 class qquart(PBase):
 175
 176     def slowimport(self):
 177         return "          import Uart16550         :: *;"
 178
 179     def slowifdecl(self):
 180         return "            interface RS232_PHY_Ifc uart{0}_coe;\n" + \
 181                "            method Bit#(1) uart{0}_intr;"
 182
 183     def num_axi_regs32(self):
 184         return 8
 185
 186     def mkslow_peripheral(self, size=0):
 187         return "        Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
 188                "                mkUart16550(clocked_by sp_clock,\n" + \
 189                "                    reset_by uart_reset, sp_clock, sp_reset);"
 190
 191     def _mk_connection(self, name=None, count=0):
 192         return "uart{0}.slave_axi_uart"
 193
 194     def pinname_out(self, pname):
 195         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 196
 197     def pinname_in(self, pname):
 198         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 199
 200
 201 class rs232(PBase):
 202
 203     def slowimport(self):
 204         return "        import Uart_bs::*;\n" + \
 205                "        import RS232_modified::*;"
 206
 207     def slowifdecl(self):
 208         return "            interface RS232 uart{0}_coe;"
 209
 210     def num_axi_regs32(self):
 211         return 2
 212
 213     def mkslow_peripheral(self, size=0):
 214         return "        //Ifc_Uart_bs uart{0} <-" + \
 215                "        //       mkUart_bs(clocked_by uart_clock,\n" + \
 216                "        //          reset_by uart_reset,sp_clock, sp_reset);" +\
 217                "        Ifc_Uart_bs uart{0} <-" + \
 218                "                mkUart_bs(clocked_by sp_clock,\n" + \
 219                "                    reset_by sp_reset, sp_clock, sp_reset);"
 220
 221     def _mk_connection(self, name=None, count=0):
 222         return "uart{0}.slave_axi_uart"
 223
 224     def pinname_out(self, pname):
 225         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 226
 227     def pinname_in(self, pname):
 228         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 229
 230
 231 class twi(PBase):
 232
 233     def slowimport(self):
 234         return "        import I2C_top           :: *;"
 235
 236     def slowifdecl(self):
 237         return "            interface I2C_out twi{0}_out;\n" + \
 238                "            method Bit#(1) twi{0}_isint;"
 239
 240     def num_axi_regs32(self):
 241         return 8
 242
 243     def mkslow_peripheral(self, size=0):
 244         return "        I2C_IFC twi{0} <- mkI2CController();"
 245
 246     def _mk_connection(self, name=None, count=0):
 247         return "twi{0}.slave_i2c_axi"
 248
 249     def pinname_out(self, pname):
 250         return {'sda': 'out.sda_out',
 251                 'scl': 'out.scl_out'}.get(pname, '')
 252
 253     def pinname_in(self, pname):
 254         return {'sda': 'out.sda_in',
 255                 'scl': 'out.scl_in'}.get(pname, '')
 256
 257     def pinname_outen(self, pname):
 258         return {'sda': 'out.sda_out_en',
 259                 'scl': 'out.scl_out_en'}.get(pname, '')
 260
 261     def pinname_tweak(self, pname, typ, txt):
 262         if typ == 'outen':
 263             return "pack({0})".format(txt)
 264         return txt
 265
 266
 267 class qspi(PBase):
 268
 269     def slowimport(self):
 270         return "        import qspi              :: *;"
 271
 272     def slowifdecl(self):
 273         return "            interface QSPI_out qspi{0}_out;\n" + \
 274                "            method Bit#(1) qspi{0}_isint;"
 275
 276     def num_axi_regs32(self):
 277         return 13
 278
 279     def mkslow_peripheral(self, size=0):
 280         return "        Ifc_qspi qspi{0} <-  mkqspi();"
 281
 282     def _mk_connection(self, name=None, count=0):
 283         return "qspi{0}.slave"
 284
 285     def pinname_out(self, pname):
 286         return {'ck': 'out.clk_o',
 287                 'nss': 'out.ncs_o',
 288                 'io0': 'out.io_o[0]',
 289                 'io1': 'out.io_o[1]',
 290                 'io2': 'out.io_o[2]',
 291                 'io3': 'out.io_o[3]',
 292                 }.get(pname, '')
 293
 294     def pinname_outen(self, pname):
 295         return {'ck': 1,
 296                 'nss': 1,
 297                 'io0': 'out.io_enable[0]',
 298                 'io1': 'out.io_enable[1]',
 299                 'io2': 'out.io_enable[2]',
 300                 'io3': 'out.io_enable[3]',
 301                 }.get(pname, '')
 302
 303     def mk_pincon(self, name, count):
 304         ret = [PBase.mk_pincon(self, name, count)]
 305         # special-case for gpio in, store in a temporary vector
 306         plen = len(self.peripheral.pinspecs)
 307         ret.append("    // XXX NSS and CLK are hard-coded master")
 308         ret.append("    // TODO: must add qspi slave-mode")
 309         ret.append("    // all ins done in one rule from 4-bitfield")
 310         ret.append("    rule con_%s%d_io_in;" % (name, count))
 311         ret.append("       {0}{1}.out.io_i({{".format(name, count))
 312         for i, p in enumerate(self.peripheral.pinspecs):
 313             typ = p['type']
 314             pname = p['name']
 315             if not pname.startswith('io'):
 316                 continue
 317             idx = pname[1:]
 318             n = name
 319             sname = self.peripheral.pname(pname).format(count)
 320             ps = "pinmux.peripheral_side.%s_in" % sname
 321             comma = '' if i == 5 else ','
 322             ret.append("            {0}{1}".format(ps, comma))
 323         ret.append("        });")
 324         ret.append("    endrule")
 325         return '\n'.join(ret)
 326
 327
 328 class pwm(PBase):
 329
 330     def slowimport(self):
 331         return "        import pwm::*;"
 332
 333     def slowifdecl(self):
 334         return "        interface PWMIO pwm{0}_io;"
 335
 336     def num_axi_regs32(self):
 337         return 4
 338
 339     def mkslow_peripheral(self, size=0):
 340         return "        Ifc_PWM_bus pwm{0} <- mkPWM_bus(sp_clock);"
 341
 342     def _mk_connection(self, name=None, count=0):
 343         return "pwm{0}.axi4_slave"
 344
 345     def pinname_out(self, pname):
 346         return {'out': 'pwm_io.pwm_o'}.get(pname, '')
 347
 348
 349 class gpio(PBase):
 350
 351     def slowimport(self):
 352         return "     import pinmux::*;\n" + \
 353                "     import mux::*;\n" + \
 354                "     import gpio::*;\n"
 355
 356     def slowifdeclmux(self):
 357         size = len(self.peripheral.pinspecs)
 358         return "    interface GPIO_config#(%d) pad_config{0};" % size
 359
 360     def num_axi_regs32(self):
 361         return 2
 362
 363     def axi_slave_idx(self, idx, name, ifacenum):
 364         """ generates AXI slave number definition, except
 365             GPIO also has a muxer per bank
 366         """
 367         name = name.upper()
 368         mname = 'mux' + name[4:]
 369         mname = mname.upper()
 370         print "AXIslavenum", name,  mname
 371         (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
 372         (ret2, x) = PBase.axi_slave_idx(self, idx+1, mname, ifacenum)
 373         return ("%s\n%s" % (ret, ret2), 2)
 374
 375     def mkslow_peripheral(self, size=0):
 376         print "gpioslow", self.peripheral,  dir(self.peripheral)
 377         size = len(self.peripheral.pinspecs)
 378         return "        MUX#(%d) mux{0} <- mkmux();\n" % size + \
 379                "        GPIO#(%d) gpio{0} <- mkgpio();" % size
 380
 381     def mk_connection(self, count):
 382         print "GPIO mk_conn", self.name, count
 383         res = []
 384         dname = self.mksuffix(self.name, count)
 385         for i, n in enumerate(['gpio' + dname, 'mux' + dname]):
 386             res.append(PBase.mk_connection(self, count, n))
 387         return '\n'.join(res)
 388
 389     def _mk_connection(self, name=None, count=0):
 390         n = self.mksuffix(name, count)
 391         if name.startswith('gpio'):
 392             return "gpio{0}.axi_slave".format(n)
 393         if name.startswith('mux'):
 394             return "mux{0}.axi_slave".format(n)
 395
 396     def mksuffix(self, name, i):
 397         if name.startswith('mux'):
 398             return name[3:]
 399         return name[4:]
 400
 401     def mk_cellconn(self, cellnum, name, count):
 402         ret = []
 403         bank = self.mksuffix(name, count)
 404         txt = "       pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
 405         for p in self.peripheral.pinspecs:
 406             ret.append(txt.format(cellnum, bank, p['name'][1:]))
 407             cellnum += 1
 408         return ("\n".join(ret), cellnum)
 409
 410     def pinname_out(self, pname):
 411         return "func.gpio_out[{0}]".format(pname[1:])
 412
 413     def pinname_outen(self, pname):
 414         return {'sda': 'out.sda_outen',
 415                 'scl': 'out.scl_outen'}.get(pname, '')
 416
 417     def mk_pincon(self, name, count):
 418         ret = [PBase.mk_pincon(self, name, count)]
 419         # special-case for gpio in, store in a temporary vector
 420         plen = len(self.peripheral.pinspecs)
 421         ret.append("    rule con_%s%d_in;" % (name, count))
 422         ret.append("       Vector#({0},Bit#(1)) temp;".format(plen))
 423         for p in self.peripheral.pinspecs:
 424             typ = p['type']
 425             pname = p['name']
 426             idx = pname[1:]
 427             n = name
 428             sname = self.peripheral.pname(pname).format(count)
 429             ps = "pinmux.peripheral_side.%s_in" % sname
 430             ret.append("        temp[{0}]={1};".format(idx, ps))
 431         ret.append("        {0}.func.gpio_in(temp);".format(name))
 432         ret.append("    endrule")
 433         return '\n'.join(ret)
 434
 435
 436 axi_slave_declarations = """\
 437 typedef  0  SlowMaster;
 438 {0}
 439 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 440               CLINT_slave_num;
 441 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 442               Plic_slave_num;
 443 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 444               AxiExp1_slave_num;
 445 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 446 """
 447
 448 pinmux_cellrule = """\
 449     rule connect_select_lines_pinmux;
 450 {0}
 451     endrule
 452 """
 453
 454
 455 class CallFn(object):
 456     def __init__(self, peripheral, name):
 457         self.peripheral = peripheral
 458         self.name = name
 459
 460     def __call__(self, *args):
 461         #print "__call__", self.name, self.peripheral.slow, args
 462         if not self.peripheral.slow:
 463             return ''
 464         return getattr(self.peripheral.slow, self.name)(*args[1:])
 465
 466
 467 class PeripheralIface(object):
 468     def __init__(self, ifacename):
 469         self.slow = None
 470         slow = slowfactory.getcls(ifacename)
 471         print "Iface", ifacename, slow
 472         if slow:
 473             self.slow = slow(ifacename)
 474             self.slow.peripheral = self
 475         for fname in ['slowimport', 'slowifdecl', 'slowifdeclmux',
 476                       'mkslow_peripheral',
 477                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
 478             fn = CallFn(self, fname)
 479             setattr(self, fname, types.MethodType(fn, self))
 480
 481         #print "PeripheralIface"
 482         #print dir(self)
 483
 484     def mksuffix(self, name, i):
 485         if self.slow is None:
 486             return i
 487         return self.slow.mksuffix(name, i)
 488
 489     def axi_reg_def(self, start, count):
 490         if not self.slow:
 491             return ('', 0)
 492         return self.slow.axi_reg_def(start, self.ifacename, count)
 493
 494     def axi_slave_idx(self, start, count):
 495         if not self.slow:
 496             return ('', 0)
 497         return self.slow.axi_slave_idx(start, self.ifacename, count)
 498
 499     def axi_addr_map(self, count):
 500         if not self.slow:
 501             return ''
 502         return self.slow.axi_addr_map(self.ifacename, count)
 503
 504
 505 class PeripheralInterfaces(object):
 506     def __init__(self):
 507         pass
 508
 509     def slowimport(self, *args):
 510         ret = []
 511         for (name, count) in self.ifacecount:
 512             #print "slowimport", name, self.data[name].slowimport
 513             ret.append(self.data[name].slowimport())
 514         return '\n'.join(list(filter(None, ret)))
 515
 516     def slowifdeclmux(self, *args):
 517         ret = []
 518         for (name, count) in self.ifacecount:
 519             for i in range(count):
 520                 ret.append(self.data[name].slowifdeclmux().format(i, name))
 521         return '\n'.join(list(filter(None, ret)))
 522
 523     def slowifdecl(self, *args):
 524         ret = []
 525         for (name, count) in self.ifacecount:
 526             for i in range(count):
 527                 ret.append(self.data[name].slowifdecl().format(i, name))
 528         return '\n'.join(list(filter(None, ret)))
 529
 530     def axi_reg_def(self, *args):
 531         ret = []
 532         start = 0x00011100  # start of AXI peripherals address
 533         for (name, count) in self.ifacecount:
 534             for i in range(count):
 535                 x = self.data[name].axi_reg_def(start, i)
 536                 #print ("ifc", name, x)
 537                 (rdef, offs) = x
 538                 ret.append(rdef)
 539                 start += offs
 540         return '\n'.join(list(filter(None, ret)))
 541
 542     def axi_slave_idx(self, *args):
 543         ret = []
 544         start = 0
 545         for (name, count) in self.ifacecount:
 546             for i in range(count):
 547                 (rdef, offs) = self.data[name].axi_slave_idx(start, i)
 548                 #print ("ifc", name, rdef, offs)
 549                 ret.append(rdef)
 550                 start += offs
 551         ret.append("typedef %d LastGen_slave_num;" % (start - 1))
 552         decls = '\n'.join(list(filter(None, ret)))
 553         return axi_slave_declarations.format(decls)
 554
 555     def axi_addr_map(self, *args):
 556         ret = []
 557         for (name, count) in self.ifacecount:
 558             for i in range(count):
 559                 ret.append(self.data[name].axi_addr_map(i))
 560         return '\n'.join(list(filter(None, ret)))
 561
 562     def mkslow_peripheral(self, *args):
 563         ret = []
 564         for (name, count) in self.ifacecount:
 565             for i in range(count):
 566                 print "mkslow", name, count
 567                 x = self.data[name].mkslow_peripheral()
 568                 print name, count, x
 569                 suffix = self.data[name].mksuffix(name, i)
 570                 ret.append(x.format(suffix))
 571         return '\n'.join(list(filter(None, ret)))
 572
 573     def mk_connection(self, *args):
 574         ret = []
 575         for (name, count) in self.ifacecount:
 576             for i in range(count):
 577                 print "mk_conn", name, i
 578                 txt = self.data[name].mk_connection(i)
 579                 if name == 'gpioa':
 580                     print "txt", txt
 581                     print self.data[name].mk_connection
 582                 ret.append(txt)
 583         return '\n'.join(list(filter(None, ret)))
 584
 585     def mk_cellconn(self):
 586         ret = []
 587         cellcount = 0
 588         for (name, count) in self.ifacecount:
 589             for i in range(count):
 590                 res = self.data[name].mk_cellconn(cellcount, name, i)
 591                 if not res:
 592                     continue
 593                 (txt, cellcount) = res
 594                 ret.append(txt)
 595         ret = '\n'.join(list(filter(None, ret)))
 596         return pinmux_cellrule.format(ret)
 597
 598     def mk_pincon(self):
 599         ret = []
 600         for (name, count) in self.ifacecount:
 601             for i in range(count):
 602                 txt = self.data[name].mk_pincon(name, i)
 603                 ret.append(txt)
 604         return '\n'.join(list(filter(None, ret)))
 605
 606
 607 class PFactory(object):
 608     def getcls(self, name):
 609         for k, v in {'uart': uart,
 610                      'rs232': rs232,
 611                      'twi': twi,
 612                      'qspi': qspi,
 613                      'pwm': pwm,
 614                      'gpio': gpio
 615                      }.items():
 616             if name.startswith(k):
 617                 return v
 618         return None
 619
 620
 621 slowfactory = PFactory()
 622
 623 if __name__ == '__main__':
 624     p = uart('uart')
 625     print p.slowimport()
 626     print p.slowifdecl()
 627     i = PeripheralIface('uart')
 628     print i, i.slow
 629     i = PeripheralIface('gpioa')
 630     print i, i.slow