src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 import GetPut::*;
  43 import Vector::*;
  44
  45 '''
  46 footer = '''
  47    endmodule
  48 endpackage
  49 '''
  50
  51
  52 def pinmuxgen(pth=None, verify=True):
  53     """ populating the file with the code
  54     """
  55
  56     p = Parse(pth, verify)
  57     iocells = Interfaces()
  58     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  59     ifaces = Interfaces(pth)
  60     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  61     init(p, ifaces)
  62
  63     bp = 'bsv_src'
  64     if pth:
  65         bp = os.path.join(pth, bp)
  66     if not os.path.exists(bp):
  67         os.makedirs(bp)
  68     bl = os.path.join(bp, 'bsv_lib')
  69     if not os.path.exists(bl):
  70         os.makedirs(bl)
  71
  72     cwd = os.path.split(__file__)[0]
  73
  74     # copy over template and library files
  75     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  76                     os.path.join(bp, 'Makefile'))
  77     shutil.copyfile(os.path.join(cwd, 'Makefile.peripherals.template'),
  78                     os.path.join(bp, 'Makefile.peripherals'))
  79     cwd = os.path.join(cwd, 'bsv_lib')
  80     for fname in []:
  81         shutil.copyfile(os.path.join(cwd, fname),
  82                         os.path.join(bl, fname))
  83
  84     bus = os.path.join(bp, 'busenable.bsv')
  85     pmp = os.path.join(bp, 'pinmux.bsv')
  86     bvp = os.path.join(bp, 'bus.bsv')
  87     idef = os.path.join(bp, 'instance_defines.bsv')
  88     slow = os.path.join(bp, 'slow_peripherals.bsv')
  89     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  90
  91     slowmf = os.path.join(bp, 'slow_memory_map.bsv')
  92     slowmt = os.path.join(cwd, 'slow_tuple2_template.bsv')
  93
  94     slowid = os.path.join(bp, 'slow_instance_defines.bsv')
  95     slowit = os.path.join(cwd, 'slow_instance_defines_template.bsv')
  96
  97     fastmf = os.path.join(bp, 'fast_memory_map.bsv')
  98     fastmt = os.path.join(cwd, 'fast_tuple2_template.bsv')
  99
 100     fastid = os.path.join(bp, 'fast_instance_defines.bsv')
 101     fastit = os.path.join(cwd, 'fast_instance_defines_template.bsv')
 102
 103     soc = os.path.join(bp, 'socgen.bsv')
 104     soct = os.path.join(cwd, 'soc_template.bsv')
 105
 106     write_pmp(pmp, p, ifaces, iocells)
 107     write_bvp(bvp, p, ifaces)
 108     write_bus(bus, p, ifaces)
 109     write_instances(idef, p, ifaces)
 110     write_slow(slow, slowt, slowmf, slowmt, slowid, slowit, p, ifaces, iocells)
 111     write_soc(soc, soct, fastmf, fastmt, fastid, fastit, p, ifaces, iocells)
 112
 113
 114 def write_slow(slow, slowt, slowmf, slowmt, slowid, slowit, p, ifaces, iocells):
 115     """ write out the slow_peripherals.bsv file.
 116         joins all the peripherals together into one AXI Lite interface
 117     """
 118     imports = ifaces.slowimport()
 119     ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 120     regdef = ifaces.axi_reg_def()
 121     slavedecl = ifaces.axi_slave_idx()
 122     fnaddrmap = ifaces.axi_addr_map()
 123     mkslow = ifaces.mkslow_peripheral()
 124     mkcon = ifaces.mk_connection()
 125     mkcellcon = ifaces.mk_cellconn()
 126     pincon = ifaces.mk_pincon()
 127     inst = ifaces.extifinstance()
 128     inst2 = ifaces.extifinstance2()
 129     mkplic = ifaces.mk_plic()
 130     numsloirqs = ifaces.mk_sloirqsdef()
 131     ifacedef = ifaces.mk_ext_ifacedef()
 132     ifacedef = ifaces.mk_ext_ifacedef()
 133     clockcon = ifaces.mk_slowclk_con()
 134
 135     with open(slow, "w") as bsv_file:
 136         with open(slowt) as f:
 137             slowt = f.read()
 138         bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
 139                                     fnaddrmap, mkslow, mkcon, mkcellcon,
 140                                     pincon, inst, mkplic,
 141                                     numsloirqs, ifacedef,
 142                                     inst2, clockcon))
 143
 144     with open(slowid, "w") as bsv_file:
 145         with open(slowit) as f:
 146             slowit = f.read()
 147         bsv_file.write(slowit.format(regdef))
 148
 149     with open(slowmf, "w") as bsv_file:
 150         with open(slowmt) as f:
 151             slowmt = f.read()
 152         bsv_file.write(slowmt.format(fnaddrmap, slavedecl))
 153
 154
 155 def write_soc(soc, soct, fastmf, fastmt, fastid, fastit, p, ifaces, iocells):
 156     """ write out the soc.bsv file.
 157         joins all the peripherals together as AXI Masters
 158     """
 159     ifaces.fastbusmode = True  # side-effects... shouldn't really do this
 160
 161     imports = ifaces.slowimport()
 162     ifdecl = ifaces.fastifdecl()
 163     regdef = ifaces.axi_fastmem_def()
 164     slavedecl = ifaces.axi_fastslave_idx()
 165     mastdecl = ifaces.axi_master_idx()
 166     fnaddrmap = ifaces.axi_fastaddr_map()
 167     mkfast = ifaces.mkfast_peripheral()
 168     mkcon = ifaces.mk_fast_connection()
 169     mkmstcon = ifaces.mk_master_connection()
 170     mkcellcon = ifaces.mk_cellconn()
 171     pincon = ifaces.mk_fast_pincon()
 172     inst = ifaces.extfastifinstance()
 173     mkplic = ifaces.mk_plic()
 174     numsloirqs = ifaces.mk_sloirqsdef()
 175     ifacedef = ifaces.mk_ext_ifacedef()
 176     dma = ifaces.mk_dma_irq()
 177     num_dmachannels = ifaces.num_dmachannels()
 178     clockcon = ifaces.mk_fastclk_con()
 179
 180     with open(soc, "w") as bsv_file:
 181         with open(soct) as f:
 182             soct = f.read()
 183         bsv_file.write(soct.format(imports, ifdecl, mkfast,
 184                                    slavedecl, mastdecl, mkcon,
 185                                    inst, dma, num_dmachannels,
 186                                    pincon, regdef, fnaddrmap,
 187                                    clockcon, mkmstcon,
 188                                    ))
 189
 190     with open(fastid, "w") as bsv_file:
 191         with open(fastit) as f:
 192             fastit = f.read()
 193         bsv_file.write(fastit.format(regdef))
 194
 195     with open(fastmf, "w") as bsv_file:
 196         with open(fastmt) as f:
 197             fastmt = f.read()
 198         bsv_file.write(fastmt.format(slavedecl, mastdecl, fnaddrmap))
 199
 200
 201 def write_bus(bus, p, ifaces):
 202     # package and interface declaration followed by
 203     # the generic io_cell definition
 204     with open(bus, "w") as bsv_file:
 205         ifaces.busfmt(bsv_file)
 206
 207
 208 def write_pmp(pmp, p, ifaces, iocells):
 209     # package and interface declaration followed by
 210     # the generic io_cell definition
 211     with open(pmp, "w") as bsv_file:
 212         bsv_file.write(header)
 213
 214         bwid_template = 'Bit#(%d)'
 215         bsv_file.write('''\
 216       (*always_ready,always_enabled*)
 217       interface MuxSelectionLines;
 218
 219       // declare the method which will capture the user pin-mux
 220       // selection values.The width of the input is dependent on the number
 221       // of muxes happening per IO. For now we have a generalized width
 222       // where each IO will have the same number of muxes.''')
 223
 224         for cell in p.muxed_cells:
 225             cellnum = cell[0]
 226             bitwidth = p.get_muxbitwidth(cellnum)
 227             if bitwidth == 0:
 228                 continue
 229             cell_bit_width = bwid_template % bitwidth
 230             bsv_file.write(mux_interface.ifacefmt(cellnum, cell_bit_width))
 231
 232         bsv_file.write("\n      endinterface\n")
 233
 234         bsv_file.write('''
 235
 236       interface IOCellSide;
 237       // declare the interface to the IO cells.
 238       // Each IO cell will have 1 input field (output from pin mux)
 239       // and an output and out-enable field (input to pinmux)''')
 240
 241         # == create method definitions for all iocell interfaces ==#
 242         iocells.ifacefmt(bsv_file)
 243
 244         # ===== finish interface definition and start module definition=======
 245         bsv_file.write("\n      endinterface\n")
 246
 247         ifaces.ifacepfmt(bsv_file)
 248         # ===== io cell definition =======
 249         bsv_file.write('''
 250       (*always_ready,always_enabled*)
 251       interface PeripheralSide;
 252       // declare the interface to the peripherals
 253       // Each peripheral's function will be either an input, output
 254       // or be bi-directional.  an input field will be an output from the
 255       // peripheral and an output field will be an input to the peripheral.
 256       // Bi-directional functions also have an output-enable (which
 257       // again comes *in* from the peripheral)''')
 258         # ==============================================================
 259
 260         # == create method definitions for all peripheral interfaces ==#
 261         ifaces.ifacefmt2(bsv_file)
 262         bsv_file.write("\n      endinterface\n")
 263
 264         # ===== finish interface definition and start module definition=======
 265         bsv_file.write('''
 266
 267    interface Ifc_pinmux;
 268       // this interface controls how each IO cell is routed.  setting
 269       // any given IO cell's mux control value will result in redirection
 270       // of not just the input or output to different peripheral functions
 271       // but also the *direction* control - if appropriate - as well.
 272       interface MuxSelectionLines mux_lines;
 273
 274       // this interface contains the inputs, outputs and direction-control
 275       // lines for all peripherals.  GPIO is considered to also be just
 276       // a peripheral because it also has in, out and direction-control.
 277       interface PeripheralSide peripheral_side;
 278
 279       // this interface is to be linked to the individual IO cells.
 280       // if looking at a "non-muxed" GPIO design, basically the
 281       // IO cell input, output and direction-control wires are cut
 282       // (giving six pairs of dangling wires, named left and right)
 283       // these iocells are routed in their place on one side ("left")
 284       // and the matching *GPIO* peripheral interfaces in/out/dir
 285       // connect to the OTHER side ("right").  the result is that
 286       // the muxer settings end up controlling the routing of where
 287       // the I/O from the IOcell actually goes.
 288       interface IOCellSide iocell_side;
 289    endinterface
 290
 291    (*synthesize*)
 292    module mkpinmux(Ifc_pinmux);
 293 ''')
 294         # ====================================================================
 295
 296         # ======================= create wire and registers =================#
 297         bsv_file.write('''
 298       // the followins wires capture the pin-mux selection
 299       // values for each mux assigned to a CELL
 300 ''')
 301         for cell in p.muxed_cells:
 302             cellnum = cell[0]
 303             bitwidth = p.get_muxbitwidth(cellnum)
 304             if bitwidth == 0:
 305                 continue
 306             cell_bit_width = bwid_template % bitwidth
 307             bsv_file.write(mux_interface.wirefmt(cellnum, cell_bit_width))
 308
 309         iocells.wirefmt(bsv_file)
 310         ifaces.wirefmt(bsv_file)
 311
 312         bsv_file.write("\n")
 313         # ====================================================================
 314         # ========================= Actual pinmuxing ========================#
 315         bsv_file.write('''
 316       /*====== This where the muxing starts for each io-cell======*/
 317       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 318       Wire#(Bit#(1)) val1<-mkDWire(1); // need a one
 319 ''')
 320         bsv_file.write(p.pinmux)
 321         bsv_file.write('''
 322       /*============================================================*/
 323 ''')
 324         # ====================================================================
 325         # ================= interface definitions for each method =============#
 326         bsv_file.write('''
 327     interface mux_lines = interface MuxSelectionLines
 328 ''')
 329         for cell in p.muxed_cells:
 330             cellnum = cell[0]
 331             bitwidth = p.get_muxbitwidth(cellnum)
 332             if bitwidth == 0:
 333                 continue
 334             cell_bit_width = bwid_template % bitwidth
 335             bsv_file.write(
 336                 mux_interface.ifacedef(
 337                     cellnum, cell_bit_width))
 338         bsv_file.write("\n    endinterface;")
 339
 340         bsv_file.write('''
 341
 342     interface iocell_side = interface IOCellSide
 343 ''')
 344         iocells.ifacedef(bsv_file)
 345         bsv_file.write("\n     endinterface;")
 346
 347         bsv_file.write('''
 348
 349      interface peripheral_side = interface PeripheralSide
 350 ''')
 351         ifaces.ifacedef2(bsv_file)
 352         bsv_file.write("\n      endinterface;")
 353
 354         bsv_file.write(footer)
 355         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 356         # ======================================================================
 357
 358
 359 def write_bvp(bvp, p, ifaces):
 360     # ######## Generate bus transactors ################
 361     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 362               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 363     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 364         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 365
 366     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 367     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 368     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 369               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 370     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 371         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 372     with open(bvp, 'w') as bsv_file:
 373         # assume here that all muxes have a 1:1 gpio
 374         cfg = []
 375         decl = []
 376         idec = []
 377         iks = sorted(ifaces.keys())
 378         for iname in iks:
 379             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 380                 continue
 381             bank = iname[4:]
 382             ifc = ifaces[iname]
 383             npins = len(ifc.pinspecs)
 384             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 385                                       0,  # USERSPACE
 386                                       bank, npins))
 387             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 388                                      0,  # USERSPACE
 389                                      bank, npins))
 390             decl.append(gpiodec.format(npins, bank))
 391             decl.append(muxdec .format(npins, bank))
 392             idec.append(gpioifc.format(bank))
 393             idec.append(muxifc.format(bank))
 394         print dir(ifaces)
 395         print ifaces.items()
 396         print dir(ifaces['gpioa'])
 397         print ifaces['gpioa'].pinspecs
 398         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 399         gpiocfg = '\n'.join(cfg)
 400         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 401     # ##################################################
 402
 403
 404 def write_instances(idef, p, ifaces):
 405     with open(idef, 'w') as bsv_file:
 406         txt = '''\
 407 `define ADDR {0}
 408 `define PADDR {2}
 409 `define DATA {1}
 410 `define Reg_width {1}
 411 `define USERSPACE 0
 412 `define RV64
 413
 414 // TODO: work out if these are needed
 415 `define PWM_AXI4Lite
 416 `define PRFDEPTH 6
 417 `define VADDR 39
 418 `define DCACHE_BLOCK_SIZE 4
 419 `define DCACHE_WORD_SIZE 8
 420 `define PERFMONITORS                            64
 421 `define DCACHE_WAYS 4
 422 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 423
 424 // CLINT
 425     `define ClintBase       'h02000000
 426     `define ClintEnd        'h020BFFFF
 427
 428 `define PLIC
 429         `define PLICBase                'h0c000000
 430         `define PLICEnd         'h10000000
 431 `define INTERRUPT_PINS 64
 432
 433 `define BAUD_RATE 130
 434 `ifdef simulate
 435   `define BAUD_RATE 5 //130 //
 436 `endif
 437 '''
 438         bsv_file.write(txt.format(p.ADDR_WIDTH,
 439                                   p.DATA_WIDTH,
 440                                   p.PADDR_WIDTH))