src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 import GetPut::*;
  43 import Vector::*;
  44
  45 '''
  46 footer = '''
  47    endmodule
  48 endpackage
  49 '''
  50
  51
  52 def pinmuxgen(pth=None, verify=True):
  53     """ populating the file with the code
  54     """
  55
  56     p = Parse(pth, verify)
  57     iocells = Interfaces()
  58     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  59     ifaces = Interfaces(pth)
  60     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  61     init(p, ifaces)
  62
  63     bp = 'bsv_src'
  64     if pth:
  65         bp = os.path.join(pth, bp)
  66     if not os.path.exists(bp):
  67         os.makedirs(bp)
  68     bl = os.path.join(bp, 'bsv_lib')
  69     if not os.path.exists(bl):
  70         os.makedirs(bl)
  71
  72     cwd = os.path.split(__file__)[0]
  73
  74     # copy over template and library files
  75     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  76                     os.path.join(bp, 'Makefile'))
  77     shutil.copyfile(os.path.join(cwd, 'Makefile.peripherals.template'),
  78                     os.path.join(bp, 'Makefile.peripherals'))
  79     cwd = os.path.join(cwd, 'bsv_lib')
  80     for fname in []:
  81         shutil.copyfile(os.path.join(cwd, fname),
  82                         os.path.join(bl, fname))
  83
  84     bus = os.path.join(bp, 'busenable.bsv')
  85     pmp = os.path.join(bp, 'pinmux.bsv')
  86     bvp = os.path.join(bp, 'bus.bsv')
  87     idef = os.path.join(bp, 'instance_defines.bsv')
  88     slow = os.path.join(bp, 'slow_peripherals.bsv')
  89     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  90
  91     slowmf = os.path.join(bp, 'slow_memory_map.bsv')
  92     slowmt = os.path.join(cwd, 'slow_tuple2_template.bsv')
  93
  94     slowid = os.path.join(bp, 'slow_instance_defines.bsv')
  95     slowit = os.path.join(cwd, 'slow_instance_defines_template.bsv')
  96
  97     fastmf = os.path.join(bp, 'fast_memory_map.bsv')
  98     fastmt = os.path.join(cwd, 'fast_tuple2_template.bsv')
  99
 100     fastid = os.path.join(bp, 'fast_instance_defines.bsv')
 101     fastit = os.path.join(cwd, 'fast_instance_defines_template.bsv')
 102
 103     soc = os.path.join(bp, 'socgen.bsv')
 104     soct = os.path.join(cwd, 'soc_template.bsv')
 105
 106     write_pmp(pmp, p, ifaces, iocells)
 107     write_bvp(bvp, p, ifaces)
 108     write_bus(bus, p, ifaces)
 109     write_instances(idef, p, ifaces)
 110     write_slow(slow, slowt, slowmf, slowmt, slowid, slowit, p, ifaces, iocells)
 111     write_soc(soc, soct, fastmf, fastmt, fastid, fastit, p, ifaces, iocells)
 112
 113
 114 def write_slow(
 115         slow,
 116         slowt,
 117         slowmf,
 118         slowmt,
 119         slowid,
 120         slowit,
 121         p,
 122         ifaces,
 123         iocells):
 124     """ write out the slow_peripherals.bsv file.
 125         joins all the peripherals together into one AXI Lite interface
 126     """
 127     imports = ifaces.slowimport()
 128     ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 129     regdef = ifaces.axi_reg_def()
 130     slavedecl = ifaces.axi_slave_idx()
 131     fnaddrmap = ifaces.axi_addr_map()
 132     mkslow = ifaces.mkslow_peripheral()
 133     mkcon = ifaces.mk_connection()
 134     mkcellcon = ifaces.mk_cellconn()
 135     pincon = ifaces.mk_pincon()
 136     inst = ifaces.extifinstance()
 137     inst2 = ifaces.extifinstance2()
 138     mkplic = ifaces.mk_plic()
 139     numsloirqs = ifaces.mk_sloirqsdef()
 140     ifacedef = ifaces.mk_ext_ifacedef()
 141     ifacedef = ifaces.mk_ext_ifacedef()
 142     clockcon = ifaces.mk_slowclk_con()
 143
 144     with open(slow, "w") as bsv_file:
 145         with open(slowt) as f:
 146             slowt = f.read()
 147         bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
 148                                     fnaddrmap, mkslow, mkcon, mkcellcon,
 149                                     pincon, inst, mkplic,
 150                                     numsloirqs, ifacedef,
 151                                     inst2, clockcon))
 152
 153     with open(slowid, "w") as bsv_file:
 154         with open(slowit) as f:
 155             slowit = f.read()
 156         bsv_file.write(slowit.format(regdef))
 157
 158     with open(slowmf, "w") as bsv_file:
 159         with open(slowmt) as f:
 160             slowmt = f.read()
 161         bsv_file.write(slowmt.format(fnaddrmap, slavedecl))
 162
 163
 164 def write_soc(soc, soct, fastmf, fastmt, fastid, fastit, p, ifaces, iocells):
 165     """ write out the soc.bsv file.
 166         joins all the peripherals together as AXI Masters
 167     """
 168     ifaces.fastbusmode = True  # side-effects... shouldn't really do this
 169
 170     imports = ifaces.slowimport()
 171     ifdecl = ifaces.fastifdecl()
 172     regdef = ifaces.axi_fastmem_def()
 173     slavedecl = ifaces.axi_fastslave_idx()
 174     mastdecl = ifaces.axi_master_idx()
 175     fnaddrmap = ifaces.axi_fastaddr_map()
 176     mkfast = ifaces.mkfast_peripheral()
 177     mkcon = ifaces.mk_fast_connection()
 178     mkmstcon = ifaces.mk_master_connection()
 179     mkcellcon = ifaces.mk_cellconn()
 180     pincon = ifaces.mk_fast_pincon()
 181     inst = ifaces.extfastifinstance()
 182     mkplic = ifaces.mk_plic()
 183     numsloirqs = ifaces.mk_sloirqsdef()
 184     ifacedef = ifaces.mk_ext_ifacedef()
 185     dma = ifaces.mk_dma_irq()
 186     num_dmachannels = ifaces.num_dmachannels()
 187     clockcon = ifaces.mk_fastclk_con()
 188
 189     with open(soc, "w") as bsv_file:
 190         with open(soct) as f:
 191             soct = f.read()
 192         bsv_file.write(soct.format(imports, ifdecl, mkfast,
 193                                    slavedecl, mastdecl, mkcon,
 194                                    inst, dma, num_dmachannels,
 195                                    pincon, regdef, fnaddrmap,
 196                                    clockcon, mkmstcon,
 197                                    ))
 198
 199     with open(fastid, "w") as bsv_file:
 200         with open(fastit) as f:
 201             fastit = f.read()
 202         bsv_file.write(fastit.format(regdef))
 203
 204     with open(fastmf, "w") as bsv_file:
 205         with open(fastmt) as f:
 206             fastmt = f.read()
 207         bsv_file.write(fastmt.format(slavedecl, mastdecl, fnaddrmap))
 208
 209
 210 def write_bus(bus, p, ifaces):
 211     # package and interface declaration followed by
 212     # the generic io_cell definition
 213     with open(bus, "w") as bsv_file:
 214         ifaces.busfmt(bsv_file)
 215
 216
 217 def write_pmp(pmp, p, ifaces, iocells):
 218     # package and interface declaration followed by
 219     # the generic io_cell definition
 220     with open(pmp, "w") as bsv_file:
 221         bsv_file.write(header)
 222
 223         bwid_template = 'Bit#(%d)'
 224         bsv_file.write('''\
 225       (*always_ready,always_enabled*)
 226       interface MuxSelectionLines;
 227
 228       // declare the method which will capture the user pin-mux
 229       // selection values.The width of the input is dependent on the number
 230       // of muxes happening per IO. For now we have a generalized width
 231       // where each IO will have the same number of muxes.''')
 232
 233         for cell in p.muxed_cells:
 234             cellnum = cell[0]
 235             bitwidth = p.get_muxbitwidth(cellnum)
 236             if bitwidth == 0:
 237                 continue
 238             cell_bit_width = bwid_template % bitwidth
 239             bsv_file.write(mux_interface.ifacefmt(cellnum, cell_bit_width))
 240
 241         bsv_file.write("\n      endinterface\n")
 242
 243         bsv_file.write('''
 244
 245       interface IOCellSide;
 246       // declare the interface to the IO cells.
 247       // Each IO cell will have 1 input field (output from pin mux)
 248       // and an output and out-enable field (input to pinmux)''')
 249
 250         # == create method definitions for all iocell interfaces ==#
 251         iocells.ifacefmt(bsv_file)
 252
 253         # ===== finish interface definition and start module definition=======
 254         bsv_file.write("\n      endinterface\n")
 255
 256         ifaces.ifacepfmt(bsv_file)
 257         # ===== io cell definition =======
 258         bsv_file.write('''
 259       (*always_ready,always_enabled*)
 260       interface PeripheralSide;
 261       // declare the interface to the peripherals
 262       // Each peripheral's function will be either an input, output
 263       // or be bi-directional.  an input field will be an output from the
 264       // peripheral and an output field will be an input to the peripheral.
 265       // Bi-directional functions also have an output-enable (which
 266       // again comes *in* from the peripheral)''')
 267         # ==============================================================
 268
 269         # == create method definitions for all peripheral interfaces ==#
 270         ifaces.ifacefmt2(bsv_file)
 271         bsv_file.write("\n      endinterface\n")
 272
 273         # ===== finish interface definition and start module definition=======
 274         bsv_file.write('''
 275
 276    interface Ifc_pinmux;
 277       // this interface controls how each IO cell is routed.  setting
 278       // any given IO cell's mux control value will result in redirection
 279       // of not just the input or output to different peripheral functions
 280       // but also the *direction* control - if appropriate - as well.
 281       interface MuxSelectionLines mux_lines;
 282
 283       // this interface contains the inputs, outputs and direction-control
 284       // lines for all peripherals.  GPIO is considered to also be just
 285       // a peripheral because it also has in, out and direction-control.
 286       interface PeripheralSide peripheral_side;
 287
 288       // this interface is to be linked to the individual IO cells.
 289       // if looking at a "non-muxed" GPIO design, basically the
 290       // IO cell input, output and direction-control wires are cut
 291       // (giving six pairs of dangling wires, named left and right)
 292       // these iocells are routed in their place on one side ("left")
 293       // and the matching *GPIO* peripheral interfaces in/out/dir
 294       // connect to the OTHER side ("right").  the result is that
 295       // the muxer settings end up controlling the routing of where
 296       // the I/O from the IOcell actually goes.
 297       interface IOCellSide iocell_side;
 298    endinterface
 299
 300    (*synthesize*)
 301    module mkpinmux(Ifc_pinmux);
 302 ''')
 303         # ====================================================================
 304
 305         # ======================= create wire and registers =================#
 306         bsv_file.write('''
 307       // the followins wires capture the pin-mux selection
 308       // values for each mux assigned to a CELL
 309 ''')
 310         for cell in p.muxed_cells:
 311             cellnum = cell[0]
 312             bitwidth = p.get_muxbitwidth(cellnum)
 313             if bitwidth == 0:
 314                 continue
 315             cell_bit_width = bwid_template % bitwidth
 316             bsv_file.write(mux_interface.wirefmt(cellnum, cell_bit_width))
 317
 318         iocells.wirefmt(bsv_file)
 319         ifaces.wirefmt(bsv_file)
 320
 321         bsv_file.write("\n")
 322         # ====================================================================
 323         # ========================= Actual pinmuxing ========================#
 324         bsv_file.write('''
 325       /*====== This where the muxing starts for each io-cell======*/
 326       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 327       Wire#(Bit#(1)) val1<-mkDWire(1); // need a one
 328 ''')
 329         bsv_file.write(p.pinmux)
 330         bsv_file.write('''
 331       /*============================================================*/
 332 ''')
 333         # ====================================================================
 334         # ================= interface definitions for each method =============#
 335         bsv_file.write('''
 336     interface mux_lines = interface MuxSelectionLines
 337 ''')
 338         for cell in p.muxed_cells:
 339             cellnum = cell[0]
 340             bitwidth = p.get_muxbitwidth(cellnum)
 341             if bitwidth == 0:
 342                 continue
 343             cell_bit_width = bwid_template % bitwidth
 344             bsv_file.write(
 345                 mux_interface.ifacedef(
 346                     cellnum, cell_bit_width))
 347         bsv_file.write("\n    endinterface;")
 348
 349         bsv_file.write('''
 350
 351     interface iocell_side = interface IOCellSide
 352 ''')
 353         iocells.ifacedef(bsv_file)
 354         bsv_file.write("\n     endinterface;")
 355
 356         bsv_file.write('''
 357
 358      interface peripheral_side = interface PeripheralSide
 359 ''')
 360         ifaces.ifacedef2(bsv_file)
 361         bsv_file.write("\n      endinterface;")
 362
 363         bsv_file.write(footer)
 364         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 365         # ======================================================================
 366
 367
 368 def write_bvp(bvp, p, ifaces):
 369     # ######## Generate bus transactors ################
 370     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 371               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 372     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 373         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 374
 375     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 376     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 377     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 378               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 379     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 380         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 381     with open(bvp, 'w') as bsv_file:
 382         # assume here that all muxes have a 1:1 gpio
 383         cfg = []
 384         decl = []
 385         idec = []
 386         iks = sorted(ifaces.keys())
 387         for iname in iks:
 388             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 389                 continue
 390             bank = iname[4:]
 391             ifc = ifaces[iname]
 392             npins = len(ifc.pinspecs)
 393             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 394                                       0,  # USERSPACE
 395                                       bank, npins))
 396             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 397                                      0,  # USERSPACE
 398                                      bank, npins))
 399             decl.append(gpiodec.format(npins, bank))
 400             decl.append(muxdec .format(npins, bank))
 401             idec.append(gpioifc.format(bank))
 402             idec.append(muxifc.format(bank))
 403         print (dir(ifaces))
 404         print (ifaces.items())
 405         print (dir(ifaces['gpioa']))
 406         print (ifaces['gpioa'].pinspecs)
 407         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 408         gpiocfg = '\n'.join(cfg)
 409         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 410     # ##################################################
 411
 412
 413 def write_instances(idef, p, ifaces):
 414     with open(idef, 'w') as bsv_file:
 415         txt = '''\
 416 `define ADDR {0}
 417 `define PADDR {2}
 418 `define DATA {1}
 419 `define Reg_width {1}
 420 `define USERSPACE 0
 421 `define RV64
 422
 423 // TODO: work out if these are needed
 424 `define PWM_AXI4Lite
 425 `define PRFDEPTH 6
 426 `define VADDR 39
 427 `define DCACHE_BLOCK_SIZE 4
 428 `define DCACHE_WORD_SIZE 8
 429 `define PERFMONITORS                            64
 430 `define DCACHE_WAYS 4
 431 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 432
 433 // CLINT
 434     `define ClintBase       'h02000000
 435     `define ClintEnd        'h020BFFFF
 436
 437 `define PLIC
 438         `define PLICBase                'h0c000000
 439         `define PLICEnd         'h10000000
 440 `define INTERRUPT_PINS 64
 441
 442 `define BAUD_RATE 130
 443 `ifdef simulate
 444   `define BAUD_RATE 5 //130 //
 445 `endif
 446 '''
 447         bsv_file.write(txt.format(p.ADDR_WIDTH,
 448                                   p.DATA_WIDTH,
 449                                   p.PADDR_WIDTH))