src/decoder/power_decoder.py

   1 from nmigen import Module, Elaboratable, Signal
   2 from power_enums import (Function, InternalOp, In1Sel, In2Sel, In3Sel,
   3                          OutSel, RC, LdstLen, CryIn, get_csv, single_bit_flags,
   4                          get_signal_name)
   5
   6
   7 class PowerDecoder(Elaboratable):
   8     def __init__(self, width, csvname):
   9         self.opcodes = get_csv(csvname)
  10         self.opcode_in = Signal(width, reset_less=True)
  11
  12         self.function_unit = Signal(Function, reset_less=True)
  13         self.internal_op = Signal(InternalOp, reset_less=True)
  14         self.in1_sel = Signal(In1Sel, reset_less=True)
  15         self.in2_sel = Signal(In2Sel, reset_less=True)
  16         self.in3_sel = Signal(In3Sel, reset_less=True)
  17         self.out_sel = Signal(OutSel, reset_less=True)
  18         self.ldst_len = Signal(LdstLen, reset_less=True)
  19         self.rc_sel = Signal(RC, reset_less=True)
  20         self.cry_in = Signal(CryIn, reset_less=True)
  21         for bit in single_bit_flags:
  22             name = get_signal_name(bit)
  23             setattr(self, name,
  24                     Signal(reset_less=True, name=name))
  25
  26     def elaborate(self, platform):
  27         m = Module()
  28         comb = m.d.comb
  29
  30         with m.Switch(self.opcode_in):
  31             for row in self.opcodes:
  32                 opcode = int(row['opcode'], 0)
  33                 if not row['unit']:
  34                     continue
  35                 with m.Case(opcode):
  36                     comb += self.function_unit.eq(Function[row['unit']])
  37                     comb += self.internal_op.eq(InternalOp[row['internal op']])
  38                     comb += self.in1_sel.eq(In1Sel[row['in1']])
  39                     comb += self.in2_sel.eq(In2Sel[row['in2']])
  40                     comb += self.in3_sel.eq(In3Sel[row['in3']])
  41                     comb += self.out_sel.eq(OutSel[row['out']])
  42                     comb += self.ldst_len.eq(LdstLen[row['ldst len']])
  43                     comb += self.rc_sel.eq(RC[row['rc']])
  44                     comb += self.cry_in.eq(CryIn[row['cry in']])
  45                     for bit in single_bit_flags:
  46                         sig = getattr(self, get_signal_name(bit))
  47                         comb += sig.eq(int(row[bit]))
  48             with m.Default():
  49                 comb += self.function_unit.eq(Function.NONE)
  50                 comb += self.internal_op.eq(InternalOp.OP_ILLEGAL)
  51                 comb += self.in1_sel.eq(0)
  52                 comb += self.in2_sel.eq(0)
  53                 comb += self.in3_sel.eq(0)
  54                 comb += self.out_sel.eq(0)
  55                 comb += self.ldst_len.eq(0)
  56                 comb += self.rc_sel.eq(0)
  57                 comb += self.cry_in.eq(0)
  58                 for bit in single_bit_flags:
  59                     sig = getattr(self, get_signal_name(bit))
  60                     comb += sig.eq(0)
  61         return m
  62
  63     def ports(self):
  64         regular = [self.opcode_in,
  65                    self.function_unit,
  66                    self.in1_sel,
  67                    self.in2_sel,
  68                    self.in3_sel,
  69                    self.out_sel,
  70                    self.ldst_len,
  71                    self.rc_sel,
  72                    self.internal_op]
  73         single_bit_ports = [getattr(self, get_signal_name(x))
  74                             for x in single_bit_flags]
  75         return regular + single_bit_ports