src/decoder/test/test_power_decoder.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay
   3 from nmigen.test.utils import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import sys
   6 import os
   7 import unittest
   8 sys.path.append("../")
   9 from power_decoder import (PowerDecoder)
  10 from power_enums import (Function, InternalOp, In1Sel, In2Sel, In3Sel,
  11                          OutSel, RC, LdstLen, CryIn, single_bit_flags,
  12                          get_signal_name)
  13
  14
  15 class DecoderTestCase(FHDLTestCase):
  16     def run_test(self, width, csvname):
  17         m = Module()
  18         comb = m.d.comb
  19         opcode = Signal(width)
  20         function_unit = Signal(Function)
  21         internal_op = Signal(InternalOp)
  22         in1_sel = Signal(In1Sel)
  23         in2_sel = Signal(In2Sel)
  24         in3_sel = Signal(In3Sel)
  25         out_sel = Signal(OutSel)
  26         rc_sel = Signal(RC)
  27         ldst_len = Signal(LdstLen)
  28         cry_in = Signal(CryIn)
  29
  30         m.submodules.dut = dut = PowerDecoder(width, csvname)
  31         comb += [dut.opcode_in.eq(opcode),
  32                  function_unit.eq(dut.function_unit),
  33                  in1_sel.eq(dut.in1_sel),
  34                  in2_sel.eq(dut.in2_sel),
  35                  in3_sel.eq(dut.in3_sel),
  36                  out_sel.eq(dut.out_sel),
  37                  rc_sel.eq(dut.rc_sel),
  38                  ldst_len.eq(dut.ldst_len),
  39                  cry_in.eq(dut.cry_in),
  40                  internal_op.eq(dut.internal_op)]
  41
  42         sim = Simulator(m)
  43
  44         def process():
  45             for row in dut.opcodes:
  46                 yield opcode.eq(int(row['opcode'], 0))
  47                 yield Delay(1e-6)
  48                 signals = [(function_unit, Function, 'unit'),
  49                            (internal_op, InternalOp, 'internal op'),
  50                            (in1_sel, In1Sel, 'in1'),
  51                            (in2_sel, In2Sel, 'in2'),
  52                            (in3_sel, In3Sel, 'in3'),
  53                            (out_sel, OutSel, 'out'),
  54                            (rc_sel, RC, 'rc'),
  55                            (cry_in, CryIn, 'cry in'),
  56                            (ldst_len, LdstLen, 'ldst len')]
  57                 for sig, enm, name in signals:
  58                     result = yield sig
  59                     expected = enm[row[name]]
  60                     msg = f"{sig.name} == {enm(result)}, expected: {expected}"
  61                     self.assertEqual(enm(result), expected, msg)
  62                 for bit in single_bit_flags:
  63                     sig = getattr(dut, get_signal_name(bit))
  64                     result = yield sig
  65                     expected = int(row[bit])
  66                     msg = f"{sig.name} == {result}, expected: {expected}"
  67                     self.assertEqual(expected, result, msg)
  68         sim.add_process(process)
  69         with sim.write_vcd("test.vcd", "test.gtkw", traces=[
  70                 opcode, function_unit, internal_op,
  71                 in1_sel, in2_sel]):
  72             sim.run()
  73
  74     def generate_ilang(self, width, csvname):
  75         prefix = os.path.splitext(csvname)[0]
  76         dut = PowerDecoder(width, csvname)
  77         vl = rtlil.convert(dut, ports=dut.ports())
  78         with open("%s_decoder.il" % prefix, "w") as f:
  79             f.write(vl)
  80
  81     def test_major(self):
  82         self.run_test(6, "major.csv")
  83
  84     def test_minor_19(self):
  85         self.run_test(3, "minor_19.csv")
  86
  87
  88 if __name__ == "__main__":
  89     unittest.main()