src/decoder/test/test_power_decoder.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay
   3 from nmigen.test.utils import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import sys
   6 import os
   7 import unittest
   8 sys.path.append("../")
   9 from power_decoder import (PowerDecoder, pdecode)
  10 from power_enums import (Function, InternalOp, In1Sel, In2Sel, In3Sel,
  11                          OutSel, RC, LdstLen, CryIn, single_bit_flags,
  12                          get_signal_name, get_csv)
  13
  14
  15 class DecoderTestCase(FHDLTestCase):
  16
  17     def run_tst(self, bitsel, csvname, minor=None, suffix=None, opint=True):
  18         m = Module()
  19         comb = m.d.comb
  20         opcode = Signal(32)
  21         function_unit = Signal(Function)
  22         internal_op = Signal(InternalOp)
  23         in1_sel = Signal(In1Sel)
  24         in2_sel = Signal(In2Sel)
  25         in3_sel = Signal(In3Sel)
  26         out_sel = Signal(OutSel)
  27         rc_sel = Signal(RC)
  28         ldst_len = Signal(LdstLen)
  29         cry_in = Signal(CryIn)
  30
  31         # opcodes = get_csv(csvname)
  32         # m.submodules.dut = dut = PowerDecoder(32, opcodes, bitsel=bitsel,
  33         #                                       opint=opint, suffix=suffix)
  34         m.submodules.dut = dut = pdecode
  35         comb += [dut.opcode_in.eq(opcode),
  36                  function_unit.eq(dut.op.function_unit),
  37                  in1_sel.eq(dut.op.in1_sel),
  38                  in2_sel.eq(dut.op.in2_sel),
  39                  in3_sel.eq(dut.op.in3_sel),
  40                  out_sel.eq(dut.op.out_sel),
  41                  rc_sel.eq(dut.op.rc_sel),
  42                  ldst_len.eq(dut.op.ldst_len),
  43                  cry_in.eq(dut.op.cry_in),
  44                  internal_op.eq(dut.op.internal_op)]
  45
  46         sim = Simulator(m)
  47         opcodes = get_csv(csvname)
  48
  49         def process():
  50             for row in opcodes:
  51                 if not row['unit']:
  52                     continue
  53                 op = row['opcode']
  54                 if not opint: # HACK: convert 001---10 to 0b00100010
  55                     op = "0b" + op.replace('-', '0')
  56                 print ("opint", opint, row['opcode'], op)
  57                 print(row)
  58                 yield opcode.eq(0)
  59                 yield opcode[bitsel[0]:bitsel[1]].eq(int(op, 0))
  60                 if minor:
  61                     print(minor)
  62                     minorbits = minor[1]
  63                     yield opcode[minorbits[0]:minorbits[1]].eq(minor[0])
  64                 yield Delay(1e-6)
  65                 signals = [(function_unit, Function, 'unit'),
  66                            (internal_op, InternalOp, 'internal op'),
  67                            (in1_sel, In1Sel, 'in1'),
  68                            (in2_sel, In2Sel, 'in2'),
  69                            (in3_sel, In3Sel, 'in3'),
  70                            (out_sel, OutSel, 'out'),
  71                            (rc_sel, RC, 'rc'),
  72                            (cry_in, CryIn, 'cry in'),
  73                            (ldst_len, LdstLen, 'ldst len')]
  74                 for sig, enm, name in signals:
  75                     result = yield sig
  76                     expected = enm[row[name]]
  77                     msg = f"{sig.name} == {enm(result)}, expected: {expected}"
  78                     self.assertEqual(enm(result), expected, msg)
  79                 for bit in single_bit_flags:
  80                     sig = getattr(dut.op, get_signal_name(bit))
  81                     result = yield sig
  82                     expected = int(row[bit])
  83                     msg = f"{sig.name} == {result}, expected: {expected}"
  84                     self.assertEqual(expected, result, msg)
  85         sim.add_process(process)
  86         prefix = os.path.splitext(csvname)[0]
  87         with sim.write_vcd("%s.vcd" % prefix, "%s.gtkw" % prefix, traces=[
  88                 opcode, function_unit, internal_op,
  89                 in1_sel, in2_sel]):
  90             sim.run()
  91
  92     def generate_ilang(self):
  93         vl = rtlil.convert(pdecode, ports=pdecode.ports())
  94         with open("decoder.il", "w") as f:
  95             f.write(vl)
  96
  97     def test_major(self):
  98         self.run_tst((26, 32), "major.csv")
  99         self.generate_ilang()
 100
 101     def test_minor_19(self):
 102         self.run_tst((1, 11), "minor_19.csv", minor=(19, (26, 32)),
 103                      suffix=(0, 5))
 104
 105     # def test_minor_19_00000(self):
 106     #     self.run_tst((1, 11), "minor_19_00000.csv")
 107
 108     def test_minor_30(self):
 109         self.run_tst((1, 5), "minor_30.csv", minor=(30, (26, 32)))
 110
 111     def test_minor_31(self):
 112         self.run_tst((1, 11), "minor_31.csv", minor=(31, (26, 32)))
 113
 114     def test_minor_58(self):
 115         self.run_tst((0, 2), "minor_58.csv", minor=(58, (26, 32)))
 116
 117     def test_minor_62(self):
 118         self.run_tst((0, 2), "minor_62.csv", minor=(62, (26, 32)))
 119
 120
 121     # #def test_minor_31_prefix(self):
 122     # #    self.run_tst(10, "minor_31.csv", suffix=(5, 10))
 123
 124     # def test_extra(self):
 125     #     self.run_tst(32, "extra.csv", opint=False)
 126     #     self.generate_ilang(32, "extra.csv", opint=False)
 127
 128
 129 if __name__ == "__main__":
 130     unittest.main()