src/decoder/test/test_power_major_decoder.py

   1 from nmigen import Module, Elaboratable, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmigen.test.utils import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import sys
   6 import unittest
   7 sys.path.append("../")
   8 from power_major_decoder import (PowerMajorDecoder, Function,
   9                                 InternalOp, major_opcodes)
  10
  11 class DecoderTestCase(FHDLTestCase):
  12     def test_function_unit(self):
  13         m = Module()
  14         comb = m.d.comb
  15         opcode = Signal(6)
  16         function_unit = Signal(Function)
  17         internal_op = Signal(InternalOp)
  18
  19         m.submodules.dut = dut = PowerMajorDecoder()
  20         comb += [dut.opcode_in.eq(opcode),
  21                  function_unit.eq(dut.function_unit),
  22                  internal_op.eq(dut.internal_op)]
  23
  24         sim = Simulator(m)
  25         def process():
  26             for row in major_opcodes:
  27                 yield opcode.eq(int(row['opcode']))
  28                 yield Delay(1e-6)
  29                 result = yield function_unit
  30                 expected = Function[row['unit']].value
  31                 self.assertEqual(expected, result)
  32
  33                 result = yield internal_op
  34                 expected = InternalOp[row['internal op']].value
  35                 self.assertEqual(expected, result)
  36         sim.add_process(process)
  37         with sim.write_vcd("test.vcd", "test.gtkw", traces=[opcode, function_unit, internal_op]):
  38             sim.run()
  39
  40     def test_ilang(self):
  41         dut = PowerMajorDecoder()
  42         vl = rtlil.convert(dut, ports=[dut.opcode_in, dut.function_unit])
  43         with open("power_major_decoder.il", "w") as f:
  44             f.write(vl)
  45
  46 if __name__ == "__main__":
  47     unittest.main()
  48