src/experiment/compalu.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Elaboratable
   4
   5 from nmutil.latch import SRLatch, latchregister
   6
   7 """ Computation Unit (aka "ALU Manager").
   8
   9     This module runs a "revolving door" set of three latches, based on
  10     * Issue
  11     * Go_Read
  12     * Go_Write
  13     where one of them cannot be set on any given cycle.
  14     (Note however that opc_l has been inverted (and qn used), due to SRLatch
  15      default reset state being "0" rather than "1")
  16
  17     * When issue is first raised, a busy signal is sent out.
  18       The src1 and src2 registers and the operand can be latched in
  19       at this point
  20
  21     * Read request is set, which is ackowledged through the Scoreboard
  22       to the priority picker, which generates (one and only one) Go_Read
  23       at a time.  One of those will (eventually) be this Computation Unit.
  24
  25     * Once Go_Read is set, the src1/src2/operand latch door shuts (locking
  26       src1/src2/operand in place), and the ALU is told to proceed.
  27
  28     * As this is currently a "demo" unit, a countdown timer is activated
  29       to simulate an ALU "pipeline", which activates "write request release",
  30       and the ALU's output is captured into a temporary register.
  31
  32     * Write request release will go through a similar process as Read request,
  33       resulting (eventually) in Go_Write being asserted.
  34
  35     * When Go_Write is asserted, two things happen: (1) the data in the temp
  36       register is placed combinatorially onto the output, and (2) the
  37       req_l latch is cleared, busy is dropped, and the Comp Unit is back
  38       through its revolving door to do another task.
  39 """
  40
  41 class ComputationUnitNoDelay(Elaboratable):
  42     def __init__(self, rwid, opwid, alu):
  43         self.rwid = rwid
  44         self.alu = alu
  45
  46         self.counter = Signal(4)
  47         self.go_rd_i = Signal(reset_less=True) # go read in
  48         self.go_wr_i = Signal(reset_less=True) # go write in
  49         self.issue_i = Signal(reset_less=True) # fn issue in
  50
  51         self.oper_i = Signal(opwid, reset_less=True) # opcode in
  52         self.src1_i = Signal(rwid, reset_less=True) # oper1 in
  53         self.src2_i = Signal(rwid, reset_less=True) # oper2 in
  54
  55         self.busy_o = Signal(reset_less=True) # fn busy out
  56         self.data_o = Signal(rwid, reset_less=True) # Dest out
  57         self.rd_rel_o = Signal(reset_less=True) # release src1/src2 request
  58         self.req_rel_o = Signal(reset_less=True) # release request out (valid_o)
  59
  60     def elaborate(self, platform):
  61         m = Module()
  62         m.submodules.alu = self.alu
  63         m.submodules.src_l = src_l = SRLatch(sync=False)
  64         m.submodules.opc_l = opc_l = SRLatch(sync=False)
  65         m.submodules.req_l = req_l = SRLatch(sync=False)
  66
  67         # This is fascinating and very important to observe that this
  68         # is in effect a "3-way revolving door".  At no time may all 3
  69         # latches be set at the same time.
  70
  71         # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
  72         m.d.sync += opc_l.s.eq(self.issue_i) # XXX NOTE: INVERTED FROM book!
  73         m.d.sync += opc_l.r.eq(self.go_wr_i) # XXX NOTE: INVERTED FROM book!
  74
  75         # src operand latch (not using go_wr_i)
  76         m.d.sync += src_l.s.eq(self.issue_i)
  77         m.d.sync += src_l.r.eq(self.go_rd_i)
  78
  79         # dest operand latch (not using issue_i)
  80         m.d.sync += req_l.s.eq(self.go_rd_i)
  81         m.d.sync += req_l.r.eq(self.go_wr_i)
  82
  83         # XXX
  84         # XXX NOTE: sync on req_rel_o and data_o due to simulation lock-up
  85         # XXX
  86
  87         # outputs
  88         m.d.comb += self.busy_o.eq(opc_l.q) # busy out
  89         m.d.comb += self.rd_rel_o.eq(src_l.q & opc_l.q) # src1/src2 req rel
  90
  91         with m.If(opc_l.qn):
  92             m.d.sync += self.counter.eq(0)
  93         with m.If(req_l.qn & opc_l.q & (self.counter == 0)):
  94             with m.If(self.oper_i == 2): # MUL, to take 5 instructions
  95                 m.d.sync += self.counter.eq(5)
  96             with m.Elif(self.oper_i == 3): # SHIFT to take 7
  97                 m.d.sync += self.counter.eq(7)
  98             with m.Else(): # ADD/SUB to take 2
  99                 m.d.sync += self.counter.eq(2)
 100         with m.If(self.counter > 1):
 101             m.d.sync += self.counter.eq(self.counter - 1)
 102         with m.If(self.counter == 1):
 103             m.d.comb += self.req_rel_o.eq(req_l.q & opc_l.q) # req release out
 104
 105         # create a latch/register for src1/src2
 106         latchregister(m, self.src1_i, self.alu.a, src_l.q)
 107         latchregister(m, self.src2_i, self.alu.b, src_l.q)
 108         #with m.If(src_l.qn):
 109         #    m.d.comb += self.alu.op.eq(self.oper_i)
 110
 111         # create a latch/register for the operand
 112         latchregister(m, self.oper_i, self.alu.op, src_l.q)
 113
 114         # and one for the output from the ALU
 115         data_r = Signal(self.rwid, reset_less=True) # Dest register
 116         latchregister(m, self.alu.o, data_r, req_l.q)
 117
 118         with m.If(self.go_wr_i):
 119             m.d.comb += self.data_o.eq(data_r)
 120
 121         return m
 122
 123 def scoreboard_sim(dut):
 124     yield dut.dest_i.eq(1)
 125     yield dut.issue_i.eq(1)
 126     yield
 127     yield dut.issue_i.eq(0)
 128     yield
 129     yield dut.src1_i.eq(1)
 130     yield dut.issue_i.eq(1)
 131     yield
 132     yield
 133     yield
 134     yield dut.issue_i.eq(0)
 135     yield
 136     yield dut.go_read_i.eq(1)
 137     yield
 138     yield dut.go_read_i.eq(0)
 139     yield
 140     yield dut.go_write_i.eq(1)
 141     yield
 142     yield dut.go_write_i.eq(0)
 143     yield
 144
 145 def test_scoreboard():
 146     dut = Scoreboard(32, 8)
 147     vl = rtlil.convert(dut, ports=dut.ports())
 148     with open("test_scoreboard.il", "w") as f:
 149         f.write(vl)
 150
 151     run_simulation(dut, scoreboard_sim(dut), vcd_name='test_scoreboard.vcd')
 152
 153 if __name__ == '__main__':
 154     test_scoreboard()