src/ieee754/fpadd/add0.py

   1 """IEEE754 Floating Point Adder Pipeline
   2
   3 Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   4
   5 """
   6
   7 from nmigen import Module, Signal, Cat, Elaboratable
   8 from nmigen.cli import main, verilog
   9
  10 from ieee754.fpcommon.fpbase import FPNumBase, FPNumBaseRecord
  11 from ieee754.fpcommon.denorm import FPSCData
  12 from ieee754.fpcommon.getop import FPPipeContext
  13
  14
  15 class FPAddStage0Data:
  16
  17     def __init__(self, pspec):
  18         width = pspec.width
  19         self.z = FPNumBaseRecord(width, False)
  20         self.out_do_z = Signal(reset_less=True)
  21         self.oz = Signal(width, reset_less=True)
  22         self.tot = Signal(self.z.m_width + 4, reset_less=True)
  23         self.ctx = FPPipeContext(pspec)
  24         self.muxid = self.ctx.muxid
  25
  26     def eq(self, i):
  27         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
  28                 self.tot.eq(i.tot), self.ctx.eq(i.ctx)]
  29
  30
  31 class FPAddStage0Mod(Elaboratable):
  32
  33     def __init__(self, pspec):
  34         self.pspec = pspec
  35         self.i = self.ispec()
  36         self.o = self.ospec()
  37
  38     def ispec(self):
  39         return FPSCData(self.pspec, True)
  40
  41     def ospec(self):
  42         return FPAddStage0Data(self.pspec)
  43
  44     def process(self, i):
  45         return self.o
  46
  47     def setup(self, m, i):
  48         """ links module to inputs and outputs
  49         """
  50         m.submodules.add0 = self
  51         m.d.comb += self.i.eq(i)
  52
  53     def elaborate(self, platform):
  54         m = Module()
  55         comb = m.d.comb
  56
  57         # store intermediate tests (and zero-extended mantissas)
  58         seq = Signal(reset_less=True)
  59         mge = Signal(reset_less=True)
  60         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
  61         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
  62         comb += [seq.eq(self.i.a.s == self.i.b.s),
  63                      mge.eq(self.i.a.m >= self.i.b.m),
  64                      am0.eq(Cat(self.i.a.m, 0)),
  65                      bm0.eq(Cat(self.i.b.m, 0))
  66                     ]
  67         # same-sign (both negative or both positive) add mantissas
  68         with m.If(~self.i.out_do_z):
  69             comb += self.o.z.e.eq(self.i.a.e)
  70             with m.If(seq):
  71                 comb += [
  72                     self.o.tot.eq(am0 + bm0),
  73                     self.o.z.s.eq(self.i.a.s)
  74                 ]
  75             # a mantissa greater than b, use a
  76             with m.Elif(mge):
  77                 comb += [
  78                     self.o.tot.eq(am0 - bm0),
  79                     self.o.z.s.eq(self.i.a.s)
  80                 ]
  81             # b mantissa greater than a, use b
  82             with m.Else():
  83                 comb += [
  84                     self.o.tot.eq(bm0 - am0),
  85                     self.o.z.s.eq(self.i.b.s)
  86             ]
  87
  88         # pass-through context
  89         comb += self.o.oz.eq(self.i.oz)
  90         comb += self.o.out_do_z.eq(self.i.out_do_z)
  91         comb += self.o.ctx.eq(self.i.ctx)
  92         return m