src/ieee754/fpadd/add0.py

   1 """IEEE754 Floating Point Adder Pipeline
   2
   3 Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   4
   5 """
   6
   7 from nmigen import Module, Signal, Cat
   8 from nmigen.cli import main, verilog
   9
  10 from ieee754.fpcommon.modbase import FPModBase
  11
  12 from ieee754.fpcommon.fpbase import FPNumBase, FPNumBaseRecord
  13 from ieee754.fpcommon.denorm import FPSCData
  14 from ieee754.fpcommon.getop import FPPipeContext
  15
  16
  17 class FPAddStage0Data:
  18
  19     def __init__(self, pspec):
  20         width = pspec.width
  21         self.z = FPNumBaseRecord(width, False)
  22         self.out_do_z = Signal(reset_less=True)
  23         self.oz = Signal(width, reset_less=True)
  24         self.tot = Signal(self.z.m_width + 4, reset_less=True) # 4 extra bits
  25         self.ctx = FPPipeContext(pspec)
  26         self.muxid = self.ctx.muxid
  27
  28     def eq(self, i):
  29         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
  30                 self.tot.eq(i.tot), self.ctx.eq(i.ctx)]
  31
  32
  33 class FPAddStage0Mod(FPModBase):
  34
  35     def __init__(self, pspec):
  36         super().__init__(pspec, "add0")
  37
  38     def ispec(self):
  39         return FPSCData(self.pspec, True)
  40
  41     def ospec(self):
  42         return FPAddStage0Data(self.pspec)
  43
  44     def elaborate(self, platform):
  45         m = Module()
  46         comb = m.d.comb
  47
  48         # store intermediate tests (and zero-extended mantissas)
  49         seq = Signal(reset_less=True)
  50         mge = Signal(reset_less=True)
  51         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
  52         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
  53         comb += [seq.eq(self.i.a.s == self.i.b.s),
  54                      mge.eq(self.i.a.m >= self.i.b.m),
  55                      am0.eq(Cat(self.i.a.m, 0)),
  56                      bm0.eq(Cat(self.i.b.m, 0))
  57                     ]
  58
  59         # same-sign (both negative or both positive) add mantissas
  60         with m.If(~self.i.out_do_z):
  61             comb += self.o.z.e.eq(self.i.a.e)
  62             with m.If(seq):
  63                 comb += [
  64                     self.o.tot.eq(am0 + bm0),
  65                     self.o.z.s.eq(self.i.a.s)
  66                 ]
  67             # a mantissa greater than b, use a
  68             with m.Elif(mge):
  69                 comb += [
  70                     self.o.tot.eq(am0 - bm0),
  71                     self.o.z.s.eq(self.i.a.s)
  72                 ]
  73             # b mantissa greater than a, use b
  74             with m.Else():
  75                 comb += [
  76                     self.o.tot.eq(bm0 - am0),
  77                     self.o.z.s.eq(self.i.b.s)
  78             ]
  79
  80         # pass-through context
  81         comb += self.o.oz.eq(self.i.oz)
  82         comb += self.o.out_do_z.eq(self.i.out_do_z)
  83         comb += self.o.ctx.eq(self.i.ctx)
  84
  85         return m