src/ieee754/fpadd/add0.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Elaboratable
   6 from nmigen.cli import main, verilog
   7
   8 from ieee754.fpcommon.fpbase import FPNumBase, FPNumBaseRecord
   9 from ieee754.fpcommon.fpbase import FPState
  10 from ieee754.fpcommon.denorm import FPSCData
  11 from ieee754.fpcommon.getop import FPPipeContext
  12
  13
  14 class FPAddStage0Data:
  15
  16     def __init__(self, pspec):
  17         width = pspec.width
  18         self.z = FPNumBaseRecord(width, False)
  19         self.out_do_z = Signal(reset_less=True)
  20         self.oz = Signal(width, reset_less=True)
  21         self.tot = Signal(self.z.m_width + 4, reset_less=True)
  22         self.ctx = FPPipeContext(pspec)
  23         self.muxid = self.ctx.muxid
  24
  25     def eq(self, i):
  26         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
  27                 self.tot.eq(i.tot), self.ctx.eq(i.ctx)]
  28
  29
  30 class FPAddStage0Mod(Elaboratable):
  31
  32     def __init__(self, pspec):
  33         self.pspec = pspec
  34         self.i = self.ispec()
  35         self.o = self.ospec()
  36
  37     def ispec(self):
  38         return FPSCData(self.pspec, True)
  39
  40     def ospec(self):
  41         return FPAddStage0Data(self.pspec)
  42
  43     def process(self, i):
  44         return self.o
  45
  46     def setup(self, m, i):
  47         """ links module to inputs and outputs
  48         """
  49         m.submodules.add0 = self
  50         m.d.comb += self.i.eq(i)
  51
  52     def elaborate(self, platform):
  53         m = Module()
  54         comb = m.d.comb
  55
  56         # store intermediate tests (and zero-extended mantissas)
  57         seq = Signal(reset_less=True)
  58         mge = Signal(reset_less=True)
  59         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
  60         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
  61         comb += [seq.eq(self.i.a.s == self.i.b.s),
  62                      mge.eq(self.i.a.m >= self.i.b.m),
  63                      am0.eq(Cat(self.i.a.m, 0)),
  64                      bm0.eq(Cat(self.i.b.m, 0))
  65                     ]
  66         # same-sign (both negative or both positive) add mantissas
  67         with m.If(~self.i.out_do_z):
  68             comb += self.o.z.e.eq(self.i.a.e)
  69             with m.If(seq):
  70                 comb += [
  71                     self.o.tot.eq(am0 + bm0),
  72                     self.o.z.s.eq(self.i.a.s)
  73                 ]
  74             # a mantissa greater than b, use a
  75             with m.Elif(mge):
  76                 comb += [
  77                     self.o.tot.eq(am0 - bm0),
  78                     self.o.z.s.eq(self.i.a.s)
  79                 ]
  80             # b mantissa greater than a, use b
  81             with m.Else():
  82                 comb += [
  83                     self.o.tot.eq(bm0 - am0),
  84                     self.o.z.s.eq(self.i.b.s)
  85             ]
  86
  87         # pass-through context
  88         comb += self.o.oz.eq(self.i.oz)
  89         comb += self.o.out_do_z.eq(self.i.out_do_z)
  90         comb += self.o.ctx.eq(self.i.ctx)
  91         return m
  92
  93
  94 class FPAddStage0(FPState):
  95     """ First stage of add.  covers same-sign (add) and subtract
  96         special-casing when mantissas are greater or equal, to
  97         give greatest accuracy.
  98     """
  99
 100     def __init__(self, pspec):
 101         FPState.__init__(self, "add_0")
 102         self.mod = FPAddStage0Mod(width)
 103         self.o = self.mod.ospec()
 104
 105     def setup(self, m, i):
 106         """ links module to inputs and outputs
 107         """
 108         self.mod.setup(m, i)
 109
 110         # NOTE: these could be done as combinatorial (merge add0+add1)
 111         m.d.sync += self.o.eq(self.mod.o)
 112
 113     def action(self, m):
 114         m.next = "add_1"