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[ieee754fpu.git] / src / ieee754 / fpadd / test / test_add_base.py
1 # FIXME: This file is on the pytest ignore list in pyproject.toml because it has borked imports
2 from random import randint
3 from operator import add
4
5 from nmigen import Module, Signal
6 from nmigen.compat.sim import run_simulation
7
8 from nmigen_add_experiment import FPADDBase, FPADDBaseMod
9
10 def get_case(dut, a, b, mid):
11 yield dut.in_mid.eq(mid)
12 yield dut.in_a.eq(a)
13 yield dut.in_b.eq(b)
14 yield dut.in_t.stb.eq(1)
15 yield
16 yield
17 yield
18 yield
19 ack = (yield dut.in_t.ack)
20 assert ack == 0
21
22 yield dut.in_t.stb.eq(0)
23
24 yield dut.out_z.ack.eq(1)
25
26 while True:
27 out_z_stb = (yield dut.out_z.stb)
28 if not out_z_stb:
29 yield
30 continue
31 out_z = yield dut.out_z.v
32 out_mid = yield dut.out_mid
33 yield dut.out_z.ack.eq(0)
34 yield
35 break
36
37 return out_z, out_mid
38
39 def check_case(dut, a, b, z, mid=None):
40 if mid is None:
41 mid = randint(0, 6)
42 out_z, out_mid = yield from get_case(dut, a, b, mid)
43 assert out_z == z, "Output z 0x%x not equal to expected 0x%x" % (out_z, z)
44 assert out_mid == mid, "Output mid 0x%x != expected 0x%x" % (out_mid, mid)
45
46
47
48 def testbench(dut):
49 yield from check_case(dut, 0x36093399, 0x7f6a12f1, 0x7f6a12f1)
50 yield from check_case(dut, 0x006CE3EE, 0x806CE3EC, 0x00000002)
51 yield from check_case(dut, 0x00000047, 0x80000048, 0x80000001)
52 yield from check_case(dut, 0x000116C2, 0x8001170A, 0x80000048)
53 yield from check_case(dut, 0x7ed01f25, 0xff559e2c, 0xfedb1d33)
54 yield from check_case(dut, 0, 0, 0)
55 yield from check_case(dut, 0xFFFFFFFF, 0xC63B800A, 0x7FC00000)
56 yield from check_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
57 #yield from check_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
58 yield from check_case(dut, 0x7F800000, 0xFF800000, 0x7FC00000)
59 yield from check_case(dut, 0x42540000, 0xC2540000, 0x00000000)
60 yield from check_case(dut, 0xC2540000, 0x42540000, 0x00000000)
61 yield from check_case(dut, 0xfe34f995, 0xff5d59ad, 0xff800000)
62 yield from check_case(dut, 0x82471f51, 0x243985f, 0x801c3790)
63 yield from check_case(dut, 0x40000000, 0xc0000000, 0x00000000)
64 yield from check_case(dut, 0x3F800000, 0x40000000, 0x40400000)
65 yield from check_case(dut, 0x40000000, 0x3F800000, 0x40400000)
66 yield from check_case(dut, 0x447A0000, 0x4488B000, 0x4502D800)
67 yield from check_case(dut, 0x463B800A, 0x42BA8A3D, 0x463CF51E)
68 yield from check_case(dut, 0x42BA8A3D, 0x463B800A, 0x463CF51E)
69 yield from check_case(dut, 0x463B800A, 0xC2BA8A3D, 0x463A0AF6)
70 yield from check_case(dut, 0xC2BA8A3D, 0x463B800A, 0x463A0AF6)
71 yield from check_case(dut, 0xC63B800A, 0x42BA8A3D, 0xC63A0AF6)
72 yield from check_case(dut, 0x42BA8A3D, 0xC63B800A, 0xC63A0AF6)
73 yield from check_case(dut, 0x7F800000, 0x00000000, 0x7F800000)
74 yield from check_case(dut, 0x00000000, 0x7F800000, 0x7F800000)
75 yield from check_case(dut, 0xFF800000, 0x00000000, 0xFF800000)
76 yield from check_case(dut, 0x00000000, 0xFF800000, 0xFF800000)
77 yield from check_case(dut, 0x7F800000, 0x7F800000, 0x7F800000)
78 yield from check_case(dut, 0xFF800000, 0xFF800000, 0xFF800000)
79 yield from check_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000)
80 yield from check_case(dut, 0x00018643, 0x00FA72A4, 0x00FBF8E7)
81 yield from check_case(dut, 0x001A2239, 0x00FA72A4, 0x010A4A6E)
82 yield from check_case(dut, 0x3F7FFFFE, 0x3F7FFFFE, 0x3FFFFFFE)
83 yield from check_case(dut, 0x7EFFFFEE, 0x7EFFFFEE, 0x7F7FFFEE)
84 yield from check_case(dut, 0x7F7FFFEE, 0xFEFFFFEE, 0x7EFFFFEE)
85 yield from check_case(dut, 0x7F7FFFEE, 0x756CA884, 0x7F7FFFFD)
86 yield from check_case(dut, 0x7F7FFFEE, 0x758A0CF8, 0x7F7FFFFF)
87 yield from check_case(dut, 0x42500000, 0x51A7A358, 0x51A7A358)
88 yield from check_case(dut, 0x51A7A358, 0x42500000, 0x51A7A358)
89 yield from check_case(dut, 0x4E5693A4, 0x42500000, 0x4E5693A5)
90 yield from check_case(dut, 0x42500000, 0x4E5693A4, 0x4E5693A5)
91
92 if __name__ == '__main__':
93 dut = FPADDBaseMod(width=32, id_wid=5, single_cycle=True)
94 run_simulation(dut, testbench(dut), vcd_name="test_add.vcd")
95