1 """ module for adjusting a mantissa and exponent so that the MSB is always 1
4 from nmigen
import Module
, Signal
, Elaboratable
5 from nmigen
.lib
.coding
import PriorityEncoder
8 class FPMSBHigh(Elaboratable
):
9 """ makes the top mantissa bit hi (i.e. shifts until it is)
11 NOTE: this does NOT do any kind of checks. do not pass in
12 zero (empty) stuff, and it's best to check if the MSB is
13 already 1 before calling it. although it'll probably work
17 * mantissa is unsigned.
20 exp = -30, mantissa = 0b00011 - output: -33, 0b11000
21 exp = 2, mantissa = 0b01111 - output: 1, 0b11110
23 def __init__(self
, m_width
, e_width
):
24 self
.m_width
= m_width
25 self
.e_width
= e_width
27 self
.m_in
= Signal(m_width
, reset_less
=True)
28 self
.e_in
= Signal((e_width
, True), reset_less
=True)
29 self
.m_out
= Signal(m_width
, reset_less
=True)
30 self
.e_out
= Signal((e_width
, True), reset_less
=True)
32 def elaborate(self
, platform
):
36 pe
= PriorityEncoder(mwid
)
39 # *sigh* not entirely obvious: count leading zeros (clz)
40 # with a PriorityEncoder: to find from the MSB
41 # we reverse the order of the bits.
42 temp
= Signal(mwid
, reset_less
=True)
43 clz
= Signal((len(self
.e_out
), True), reset_less
=True)
45 pe
.i
.eq(insel
.m
[::-1]), # inverted
46 clz
.eq(pe
.o
), # count zeros from MSB down
47 temp
.eq((self
.m_in
<< clz
)), # shift mantissa UP
48 self
.e_out
.eq(insel
.e
- clz
), # DECREASE exponent