rework roundz to use Mux
[ieee754fpu.git] / src / ieee754 / fpcommon / pack.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module, Signal
6 from nmigen.cli import main, verilog
7
8 from nmutil.pipemodbase import PipeModBase
9 from ieee754.fpcommon.fpbase import FPNumBaseRecord, FPNumBase
10 from ieee754.fpcommon.roundz import FPRoundData
11 from ieee754.fpcommon.getop import FPPipeContext
12 from ieee754.fpcommon.packdata import FPPackData
13
14
15 class FPPackMod(PipeModBase):
16
17 def __init__(self, pspec):
18 super().__init__(pspec, "pack")
19
20 def ispec(self):
21 return FPRoundData(self.pspec)
22
23 def ospec(self):
24 return FPPackData(self.pspec)
25
26 def elaborate(self, platform):
27 m = Module()
28 comb = m.d.comb
29
30 z = FPNumBaseRecord(self.pspec.width, False, name="z")
31 m.submodules.pack_in_z = in_z = FPNumBase(self.i.z)
32
33 with m.If(~self.i.out_do_z):
34 with m.If(in_z.is_overflowed):
35 comb += z.inf(self.i.z.s)
36 with m.Else():
37 comb += z.create(self.i.z.s, self.i.z.e, self.i.z.m)
38 with m.Else():
39 comb += z.v.eq(self.i.oz)
40
41 comb += self.o.ctx.eq(self.i.ctx)
42 comb += self.o.z.eq(z.v)
43
44 return m