src/ieee754/fpdiv/div0.py

   1 """IEEE754 Floating Point Divider
   2
   3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
   4 """
   5
   6 from nmigen import Module, Signal, Cat, Elaboratable, Const
   7 from nmigen.cli import main, verilog
   8
   9 from ieee754.fpcommon.fpbase import (FPNumBaseRecord, Overflow)
  10 from ieee754.fpcommon.fpbase import FPState
  11 from ieee754.fpcommon.denorm import FPSCData
  12 from ieee754.fpcommon.getop import FPPipeContext
  13 from ieee754.div_rem_sqrt_rsqrt.div_pipe import DivPipeInputData
  14
  15
  16 class FPDivStage0Mod(Elaboratable):
  17
  18     def __init__(self, pspec):
  19         self.pspec = pspec
  20         self.i = self.ispec()
  21         self.o = self.ospec()
  22
  23     def ispec(self):
  24         return FPSCData(self.pspec, False)
  25
  26     def ospec(self):
  27         return DivPipeInputData(self.pspec)
  28
  29     def process(self, i):
  30         return self.o
  31
  32     def setup(self, m, i):
  33         """ links module to inputs and outputs
  34         """
  35         m.submodules.div0 = self
  36         m.d.comb += self.i.eq(i)
  37
  38     def elaborate(self, platform):
  39         m = Module()
  40
  41         # XXX TODO, actual DIV code here.  this class would be
  42         # "step one" which takes the pre-normalised data (see ispec) and
  43         # *begins* the processing phase (enters the massive DIV
  44         # pipeline chain) - see ospec.
  45
  46         # INPUT SPEC: FPSCData
  47         # OUTPUT SPEC: DivPipeInputData
  48
  49         # NOTE: this stage does *NOT* do *ACTUAL* DIV processing,
  50         # it is PURELY the *ENTRY* point into the chain, performing
  51         # "preparation" work.
  52
  53         with m.If(~self.i.out_do_z):
  54             # do conversion here, of both self.i.a and self.i.b,
  55             # into DivPipeInputData dividend and divisor.
  56
  57             if self.pspec.width == 16:
  58                 extra = 3
  59             elif self.pspec.width == 32:
  60                 extra = 4
  61             elif self.pspec.width == 64:
  62                 extra = 3
  63             # the mantissas, having been de-normalised (and containing
  64             # a "1" in the MSB) represent numbers in the range 0.5 to
  65             # 0.9999999-recurring.  the min and max range of the
  66             # result is therefore 0.4999999 (0.5/0.99999) and 1.9999998
  67             # (0.99999/0.5).
  68
  69             # zero-extend the mantissas (room for sticky/guard)
  70             # plus the extra MSB.  See DivPipeBaseStage.get_core_config
  71             am0 = Signal(len(self.i.a.m)+3, reset_less=True)
  72             bm0 = Signal(len(self.i.b.m)+3, reset_less=True)
  73             m.d.comb += [
  74                          am0.eq(Cat(0,0,0,self.i.a.m, 0)),
  75                          bm0.eq(Cat(0,0,0,self.i.b.m, 0)),
  76                          #am0.eq(0x392),
  77                          #bm0.eq(0x1110),
  78                         ]
  79
  80             m.d.comb += [self.o.z.e.eq(self.i.a.e - self.i.b.e + 1),
  81                          self.o.z.s.eq(self.i.a.s ^ self.i.b.s),
  82                          self.o.dividend[len(self.i.a.m)+extra:].eq(am0), # TODO: check
  83                          self.o.divisor_radicand.eq(bm0), # TODO: check
  84                          self.o.operation.eq(Const(0)) # TODO check: DIV
  85                 ]
  86
  87         # these are required and must not be touched
  88         m.d.comb += self.o.oz.eq(self.i.oz)
  89         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
  90         m.d.comb += self.o.ctx.eq(self.i.ctx)
  91
  92         return m
  93
  94
  95 class FPDivStage0(FPState):
  96     """ First stage of div.
  97     """
  98
  99     def __init__(self, pspec):
 100         FPState.__init__(self, "divider_0")
 101         self.mod = FPDivStage0Mod(pspec)
 102         self.o = self.mod.ospec()
 103
 104     def setup(self, m, i):
 105         """ links module to inputs and outputs
 106         """
 107         self.mod.setup(m, i)
 108
 109         # NOTE: these could be done as combinatorial (merge div0+div1)
 110         m.d.sync += self.o.eq(self.mod.o)
 111
 112     def action(self, m):
 113         m.next = "divider_1"