add cookie-cut FPDIV
[ieee754fpu.git] / src / ieee754 / fpdiv / divstages.py
1 # IEEE Floating Point Divider
2
3 from nmigen import Module
4 from nmigen.cli import main, verilog
5
6 from nmutil.singlepipe import (StageChain, SimpleHandshake)
7
8 from ieee754.fpcommon.fpbase import FPState
9 from ieee754.fpcommon.denorm import FPSCData
10 from ieee754.fpcommon.postcalc import FPAddStage1Data
11
12 # TODO: write these
13 from .div0 import FPDivStage0Mod
14 from .div1 import FPDivStage1Mod
15
16
17 class FPDivStages(FPState, SimpleHandshake):
18
19 def __init__(self, width, id_wid):
20 FPState.__init__(self, "align")
21 self.width = width
22 self.id_wid = id_wid
23 SimpleHandshake.__init__(self, self) # pipeline is its own stage
24 self.m1o = self.ospec()
25
26 def ispec(self):
27 return FPSCData(self.width, self.id_wid, False)
28
29 def ospec(self):
30 return FPAddStage1Data(self.width, self.id_wid) # AddStage1 ospec
31
32 def setup(self, m, i):
33 """ links module to inputs and outputs
34 """
35
36 # chain DivStage0 and DivStage1
37 m0mod = FPDivStage0Mod(self.width, self.id_wid)
38 m1mod = FPDivStage1Mod(self.width, self.id_wid)
39
40 chain = StageChain([m0mod, m1mod])
41 chain.setup(m, i)
42
43 self.o = m1mod.o
44
45 def process(self, i):
46 return self.o
47
48 def action(self, m):
49 m.d.sync += self.m1o.eq(self.process(None))
50 m.next = "normalise_1"
51
52