1 """IEEE754 Floating Point pipelined Divider
3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
7 from nmigen
import Module
8 from nmigen
.cli
import main
, verilog
10 from nmutil
.singlepipe
import (StageChain
, SimpleHandshake
)
12 from ieee754
.fpcommon
.fpbase
import FPState
13 from ieee754
.fpcommon
.denorm
import FPSCData
14 from ieee754
.fpcommon
.postcalc
import FPAddStage1Data
17 from .div0
import FPDivStage0Mod
18 from .div1
import FPDivStage1Mod
19 from .div2
import FPDivStage2Mod
22 class FPDivStages(FPState
, SimpleHandshake
):
24 def __init__(self
, width
, id_wid
):
25 FPState
.__init
__(self
, "align")
28 SimpleHandshake
.__init
__(self
, self
) # pipeline is its own stage
29 self
.m1o
= self
.ospec()
32 return FPSCData(self
.width
, self
.id_wid
, False)
35 return FPAddStage1Data(self
.width
, self
.id_wid
) # AddStage1 ospec
37 def setup(self
, m
, i
):
38 """ links module to inputs and outputs
41 # TODO. clearly, this would be a for-loop, here, creating
42 # a huge number of stages (if radix-2 is used). interestingly
43 # the number of stages will be data-dependent.
44 divstages
= [FPDivStage0Mod(self
.width
, self
.id_wid
)]
45 for i
in range(self
.width
): # XXX TODO: work out actual number needed
46 divstages
.append(FPDivStage1Mod(self
.width
, self
.id_wid
))
47 divstages
.append(FPDivStage2Mod(self
.width
, self
.id_wid
))
49 chain
= StageChain(divstages
)
58 m
.d
.sync
+= self
.m1o
.eq(self
.process(None))
59 m
.next
= "normalise_1"