src/ieee754/fpdiv/pipeline.py

   1 """IEEE Floating Point Divider Pipeline
   2
   3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
   4
   5 Stack looks like this:
   6
   7 scnorm   - FPDIVSpecialCasesDeNorm ispec FPADDBaseData
   8 ------                             ospec FPSCData
   9
  10                 StageChain: FPDIVSpecialCasesMod,
  11                             FPAddDeNormMod
  12
  13 pipediv0 - FPDivStagesSetup        ispec FPSCData
  14 --------                           ospec DivPipeInterstageData
  15
  16                 StageChain: FPDivStage0Mod,
  17                             DivPipeSetupStage,
  18                             DivPipeCalculateStage,
  19                             ...
  20                             DivPipeCalculateStage
  21
  22 pipediv1 - FPDivStagesIntermediate ispec DivPipeInterstageData
  23 --------                           ospec DivPipeInterstageData
  24
  25                 StageChain: DivPipeCalculateStage,
  26                             ...
  27                             DivPipeCalculateStage
  28 ...
  29 ...
  30
  31 pipediv5 - FPDivStageFinal         ispec FPDivStage0Data
  32 --------                           ospec FPAddStage1Data
  33
  34                 StageChain: DivPipeCalculateStage,
  35                             ...
  36                             DivPipeCalculateStage,
  37                             DivPipeFinalStage,
  38                             FPDivStage2Mod
  39
  40 normpack - FPNormToPack            ispec FPAddStage1Data
  41 --------                           ospec FPPackData
  42
  43                 StageChain: Norm1ModSingle,
  44                             RoundMod,
  45                             CorrectionsMod,
  46                             PackMod
  47
  48 the number of combinatorial StageChains (n_comb_stages) in
  49 FPDivStages is an argument arranged to get the length of the whole
  50 pipeline down to sane numbers.
  51
  52 the reason for keeping the number of stages down is that for every
  53 pipeline clock delay, a corresponding ReservationStation is needed.
  54 if there are 24 pipeline stages, we need a whopping TWENTY FOUR
  55 RS's.  that's far too many.  6 is just about an acceptable number.
  56 even 8 is starting to get alarmingly high.
  57 """
  58
  59 from nmigen import Module
  60 from nmigen.cli import main, verilog
  61
  62 from nmutil.singlepipe import ControlBase
  63 from nmutil.concurrentunit import ReservationStations, num_bits
  64
  65 from ieee754.fpcommon.getop import FPADDBaseData
  66 from ieee754.fpcommon.denorm import FPSCData
  67 from ieee754.fpcommon.fpbase import FPFormat
  68 from ieee754.fpcommon.pack import FPPackData
  69 from ieee754.fpcommon.normtopack import FPNormToPack
  70 from ieee754.fpdiv.specialcases import FPDIVSpecialCasesDeNorm
  71 from ieee754.fpdiv.divstages import (FPDivStagesSetup,
  72                                      FPDivStagesIntermediate,
  73                                      FPDivStagesFinal)
  74 from ieee754.pipeline import PipelineSpec
  75 from ieee754.div_rem_sqrt_rsqrt.core import DivPipeCoreConfig
  76
  77
  78 class FPDIVBasePipe(ControlBase):
  79     def __init__(self, pspec):
  80         self.pspec = pspec
  81         ControlBase.__init__(self)
  82
  83         pipechain = []
  84         max_n_comb_stages = 3  # TODO (depends on how many RS's we want)
  85         # to which the answer: "as few as possible"
  86         # is required.  too many ReservationStations
  87         # means "big problems".
  88
  89         # XXX BUG - subtracting 4 from number of stages stops assert
  90         # probably related to having to add 4 in FPDivMuxInOut
  91         radix = pspec.log2_radix
  92         n_stages = pspec.core_config.n_stages // max_n_comb_stages
  93         stage_idx = 0
  94
  95         for i in range(n_stages):
  96
  97             n_comb_stages = max_n_comb_stages
  98             # needs to convert input from pipestart ospec
  99             if i == 0:
 100                 kls = FPDivStagesSetup
 101                 #n_comb_stages -= 1  # reduce due to work done at start?
 102
 103             # needs to convert output to pipeend ispec
 104             elif i == n_stages - 1:
 105                 kls = FPDivStagesFinal
 106                 #n_comb_stages -= 1  # FIXME - reduce due to work done at end?
 107
 108             # intermediary stage
 109             else:
 110                 kls = FPDivStagesIntermediate
 111
 112             pipechain.append(kls(self.pspec, n_comb_stages, stage_idx))
 113             stage_idx += n_comb_stages # increment so that each CalcStage
 114                                        # gets a (correct) unique index
 115
 116         self.pipechain = pipechain
 117
 118         # start and end: unpack/specialcases then normalisation/packing
 119         self.pipestart = pipestart = FPDIVSpecialCasesDeNorm(self.pspec)
 120         self.pipeend = pipeend = FPNormToPack(self.pspec)
 121
 122         self._eqs = self.connect([pipestart] + pipechain + [pipeend])
 123
 124     def elaborate(self, platform):
 125         m = ControlBase.elaborate(self, platform)
 126
 127         # add submodules
 128         m.submodules.scnorm = self.pipestart
 129         for i, p in enumerate(self.pipechain):
 130             setattr(m.submodules, "pipediv%d" % i, p)
 131         m.submodules.normpack = self.pipeend
 132
 133         # ControlBase.connect creates the "eqs" needed to connect each pipe
 134         m.d.comb += self._eqs
 135
 136         return m
 137
 138 def roundup(x, mod):
 139     return x if x % mod == 0 else x + mod - x % mod
 140
 141
 142 class FPDIVMuxInOut(ReservationStations):
 143     """ Reservation-Station version of FPDIV pipeline.
 144
 145         * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
 146         * N-stage divider pipeline
 147         * fan-out on outputs (an array of FPPackData: z,mid)
 148
 149         Fan-in and Fan-out are combinatorial.
 150
 151         :op_wid: - set this to the width of an operator which can
 152                    then be used to change the behaviour of the pipeline.
 153     """
 154
 155     def __init__(self, width, num_rows, op_wid=1):
 156         self.id_wid = num_bits(width)
 157         self.pspec = PipelineSpec(width, self.id_wid, op_wid)
 158         # get the standard mantissa width, store in the pspec HOWEVER...
 159         fmt = FPFormat.standard(width)
 160         log2_radix = 2
 161
 162         # ...5 extra bits on the mantissa: MSB is zero, MSB-1 is 1
 163         # then there is guard, round and sticky at the LSB end.
 164         # also: round up to nearest radix
 165         fmt.m_width = roundup(fmt.m_width + 5, log2_radix)
 166
 167         cfg = DivPipeCoreConfig(fmt.m_width, fmt.fraction_width, log2_radix)
 168
 169         self.pspec.fpformat = fmt
 170         self.pspec.log2_radix = log2_radix
 171         self.pspec.core_config = cfg
 172
 173         # XXX TODO - a class (or function?) that takes the pspec (right here)
 174         # and creates... "something".  that "something" MUST have an eq function
 175         # new_pspec = deepcopy(self.pspec)
 176         # new_pspec.opkls = DivPipeCoreOperation
 177         # self.alu = FPDIVBasePipe(new_pspec)
 178         self.alu = FPDIVBasePipe(self.pspec)
 179         ReservationStations.__init__(self, num_rows)
 180
 181     def i_specfn(self):
 182         return FPADDBaseData(self.pspec)
 183
 184     def o_specfn(self):
 185         return FPPackData(self.pspec)