1 # IEEE Floating Point Divider Pipeline
3 from nmigen
import Module
4 from nmigen
.cli
import main
, verilog
6 from nmutil
.singlepipe
import ControlBase
7 from nmutil
.concurrentunit
import ReservationStations
, num_bits
9 from ieee754
.fpcommon
.getop
import FPADDBaseData
10 from ieee754
.fpcommon
.denorm
import FPSCData
11 from ieee754
.fpcommon
.pack
import FPPackData
12 from ieee754
.fpcommon
.normtopack
import FPNormToPack
13 from .specialcases
import FPDivSpecialCasesDeNorm
14 from .divstages
import FPDivStages
18 class FPDIVBasePipe(ControlBase
):
19 def __init__(self
, width
, id_wid
):
20 ControlBase
.__init
__(self
)
21 self
.pipe1
= FPDivSpecialCasesDeNorm(width
, id_wid
)
22 self
.pipe2
= FPDivStages(width
, id_wid
)
23 self
.pipe3
= FPNormToPack(width
, id_wid
)
25 self
._eqs
= self
.connect([self
.pipe1
, self
.pipe2
, self
.pipe3
])
27 def elaborate(self
, platform
):
28 m
= ControlBase
.elaborate(self
, platform
)
29 m
.submodules
.scnorm
= self
.pipe1
30 m
.submodules
.divstages
= self
.pipe2
31 m
.submodules
.normpack
= self
.pipe3
36 class FPDIVMuxInOut(ReservationStations
):
37 """ Reservation-Station version of FPDIV pipeline.
39 * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
40 * N-stage divider pipeline
41 * fan-out on outputs (an array of FPPackData: z,mid)
43 Fan-in and Fan-out are combinatorial.
45 def __init__(self
, width
, num_rows
):
47 self
.id_wid
= num_bits(width
)
48 self
.alu
= FPDIVBasePipe(width
, self
.id_wid
)
49 ReservationStations
.__init
__(self
, num_rows
)
52 return FPADDBaseData(self
.width
, self
.id_wid
)
55 return FPPackData(self
.width
, self
.id_wid
)