src/ieee754/fpdiv/pipeline.py

   1 """IEEE Floating Point Divider Pipeline
   2
   3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
   4
   5 Stack looks like this:
   6
   7 scnorm   - FPDIVSpecialCasesDeNorm ispec FPADDBaseData
   8 ------                             ospec FPSCData
   9
  10                 StageChain: FPDIVSpecialCasesMod,
  11                             FPAddDeNormMod
  12
  13 pipediv0 - FPDivStagesSetup        ispec FPSCData
  14 --------                           ospec DivPipeCoreInterstageData
  15
  16                 StageChain: FPDivStage0Mod,
  17                             DivPipeSetupStage,
  18                             DivPipeCalculateStage,
  19                             ...
  20                             DivPipeCalculateStage
  21
  22 pipediv1 - FPDivStagesIntermediate ispec DivPipeCoreInterstageData
  23 --------                           ospec DivPipeCoreInterstageData
  24
  25                 StageChain: DivPipeCalculateStage,
  26                             ...
  27                             DivPipeCalculateStage
  28 ...
  29 ...
  30
  31 pipediv5 - FPDivStageFinal         ispec FPDivStage0Data
  32 --------                           ospec FPAddStage1Data
  33
  34                 StageChain: DivPipeCalculateStage,
  35                             ...
  36                             DivPipeCalculateStage,
  37                             DivPipeFinalStage,
  38                             FPDivStage2Mod
  39
  40 normpack - FPNormToPack            ispec FPAddStage1Data
  41 --------                           ospec FPPackData
  42
  43                 StageChain: Norm1ModSingle,
  44                             RoundMod,
  45                             CorrectionsMod,
  46                             PackMod
  47
  48 the number of combinatorial StageChains (n_comb_stages) in
  49 FPDivStages is an argument arranged to get the length of the whole
  50 pipeline down to sane numbers.
  51
  52 the reason for keeping the number of stages down is that for every
  53 pipeline clock delay, a corresponding ReservationStation is needed.
  54 if there are 24 pipeline stages, we need a whopping TWENTY FOUR
  55 RS's.  that's far too many.  6 is just about an acceptable number.
  56 even 8 is starting to get alarmingly high.
  57 """
  58
  59 from nmigen import Module
  60 from nmigen.cli import main, verilog
  61
  62 from nmutil.singlepipe import ControlBase
  63 from nmutil.concurrentunit import ReservationStations, num_bits
  64
  65 from ieee754.fpcommon.getop import FPADDBaseData
  66 from ieee754.fpcommon.denorm import FPSCData
  67 from ieee754.fpcommon.fpbase import FPFormat
  68 from ieee754.fpcommon.pack import FPPackData
  69 from ieee754.fpcommon.normtopack import FPNormToPack
  70 from ieee754.fpdiv.specialcases import FPDIVSpecialCasesDeNorm
  71 from ieee754.fpdiv.divstages import (FPDivStagesSetup,
  72                                      FPDivStagesIntermediate,
  73                                      FPDivStagesFinal)
  74 from ieee754.pipeline import PipelineSpec
  75
  76
  77 class FPDIVBasePipe(ControlBase):
  78     def __init__(self, pspec):
  79         ControlBase.__init__(self)
  80         self.pspec = pspec
  81
  82     def elaborate(self, platform):
  83         m = ControlBase.elaborate(self, platform)
  84
  85         pipechain = []
  86         n_stages = 6      # TODO (depends on width)
  87         n_comb_stages = 3  # TODO (depends on how many RS's we want)
  88         stage_idx = 0
  89         # to which the answer: "as few as possible"
  90         # is required.  too many ReservationStations
  91         # means "big problems".
  92
  93         for i in range(n_stages):
  94
  95             # needs to convert input from pipestart ospec
  96             if i == 0:
  97                 kls = FPDivStagesSetup
  98                 n_comb_stages -= 1  # reduce due to work done at start
  99
 100             # needs to convert output to pipeend ispec
 101             elif i == n_stages - 1:
 102                 kls = FPDivStagesFinal
 103                 n_comb_stages -= 1  # FIXME - reduce due to work done at end?
 104
 105             # intermediary stage
 106             else:
 107                 kls = FPDivStagesIntermediate
 108
 109             pipechain.append(kls(self.pspec, n_comb_stages, stage_idx))
 110             stage_idx += n_comb_stages # increment so that each CalcStage
 111                                        # gets a (correct) unique index
 112
 113         # start and end: unpack/specialcases then normalisation/packing
 114         pipestart = FPDIVSpecialCasesDeNorm(self.pspec)
 115         pipeend = FPNormToPack(self.pspec)
 116
 117         # add submodules
 118         m.submodules.scnorm = pipestart
 119         for i, p in enumerate(pipechain):
 120             setattr(m.submodules, "pipediv%d" % i, p)
 121         m.submodules.normpack = pipeend
 122
 123         # ControlBase.connect creates the "eqs" needed to connect each pipe
 124         m.d.comb += self.connect([pipestart] + pipechain + [pipeend])
 125
 126         return m
 127
 128
 129 class FPDIVMuxInOut(ReservationStations):
 130     """ Reservation-Station version of FPDIV pipeline.
 131
 132         * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
 133         * N-stage divider pipeline
 134         * fan-out on outputs (an array of FPPackData: z,mid)
 135
 136         Fan-in and Fan-out are combinatorial.
 137
 138         :op_wid: - set this to the width of an operator which can
 139                    then be used to change the behaviour of the pipeline.
 140     """
 141
 142     def __init__(self, width, num_rows, op_wid=0):
 143         self.id_wid = num_bits(width)
 144         self.pspec = PipelineSpec(width, self.id_wid, op_wid)
 145         # get the standard mantissa width, store in the pspec
 146         # (used in DivPipeBaseStage.get_core_config)
 147         p = FPFormat.standard(width)
 148         self.pspec.m_width = p.m_width
 149
 150         # XXX TODO - a class (or function?) that takes the pspec (right here)
 151         # and creates... "something".  that "something" MUST have an eq function
 152         # new_pspec = deepcopy(self.pspec)
 153         # new_pspec.opkls = DivPipeCoreOperation
 154         # self.alu = FPDIVBasePipe(new_pspec)
 155         self.alu = FPDIVBasePipe(self.pspec)
 156         ReservationStations.__init__(self, num_rows)
 157
 158     def i_specfn(self):
 159         return FPADDBaseData(self.pspec)
 160
 161     def o_specfn(self):
 162         return FPPackData(self.pspec)