split out adder code (PartitionedAdder) into module, PartitionPoints too
[ieee754fpu.git] / src / ieee754 / fpmul / datastructs.py
1 """IEEE754 Floating Point Multiplier Pipeline
2
3 Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
4
5 """
6
7 from nmigen import Signal
8
9 from ieee754.fpcommon.fpbase import FPNumBaseRecord
10 from ieee754.fpcommon.getop import FPPipeContext
11
12
13 class FPMulStage0Data:
14
15 def __init__(self, pspec):
16 width = pspec.width
17 self.z = FPNumBaseRecord(width, False)
18 self.out_do_z = Signal(reset_less=True)
19 self.oz = Signal(width, reset_less=True)
20 mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
21 self.product = Signal(mw, reset_less=True)
22 self.ctx = FPPipeContext(pspec)
23 self.muxid = self.ctx.muxid
24
25 def eq(self, i):
26 return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
27 self.product.eq(i.product), self.ctx.eq(i.ctx)]
28