split out adder code (PartitionedAdder) into module, PartitionPoints too
[ieee754fpu.git] / src / ieee754 / fpmul / mulstages.py
1 # IEEE Floating Point Multiplier
2
3 from nmigen import Module
4 from nmigen.cli import main, verilog
5
6 from nmutil.singlepipe import StageChain
7
8 from nmutil.pipemodbase import PipeModBaseChain
9 from ieee754.fpcommon.denorm import FPSCData
10 from ieee754.fpcommon.postcalc import FPPostCalcData
11 from ieee754.fpmul.mul0 import FPMulStage0Mod
12 from ieee754.fpmul.mul1 import FPMulStage1Mod
13
14
15 class FPMulStages(PipeModBaseChain):
16
17 def get_chain(self):
18 # chain MulStage0 and MulStage1
19 m0mod = FPMulStage0Mod(self.pspec)
20 m1mod = FPMulStage1Mod(self.pspec)
21
22 return [m0mod, m1mod]
23