simplify dpoints computation
[ieee754fpu.git] / src / ieee754 / part / layout_experiment.py
1 #!/usr/bin/env python3
2 # SPDX-License-Identifier: LGPL-3-or-later
3 # See Notices.txt for copyright information
4 """
5 Links:
6 * https://libre-soc.org/3d_gpu/architecture/dynamic_simd/shape/
7 * https://bugs.libre-soc.org/show_bug.cgi?id=713#c20
8 * https://bugs.libre-soc.org/show_bug.cgi?id=713#c30
9 * https://bugs.libre-soc.org/show_bug.cgi?id=713#c34
10 * https://bugs.libre-soc.org/show_bug.cgi?id=713#c47
11 * https://bugs.libre-soc.org/show_bug.cgi?id=713#c22
12 * https://bugs.libre-soc.org/show_bug.cgi?id=713#c67
13 """
14
15 from nmigen import Signal, Module, Elaboratable, Mux, Cat, Shape, Repl
16 from nmigen.back.pysim import Simulator, Delay, Settle
17 from nmigen.cli import rtlil
18
19 from collections.abc import Mapping
20 from functools import reduce
21 import operator
22 from collections import defaultdict
23 from pprint import pprint
24
25 from ieee754.part_mul_add.partpoints import PartitionPoints
26
27
28 # main fn, which started out here in the bugtracker:
29 # https://bugs.libre-soc.org/show_bug.cgi?id=713#c20
30 # note that signed is **NOT** part of the layout, and will NOT
31 # be added (because it is not relevant or appropriate).
32 # sign belongs in ast.Shape and is the only appropriate location.
33 # there is absolutely nothing within this function that in any
34 # way requires a sign. it is *purely* performing numerical width
35 # computations that have absolutely nothing to do with whether the
36 # actual data is signed or unsigned.
37 def layout(elwid, vec_el_counts, lane_shapes=None, fixed_width=None):
38 """calculate a SIMD layout.
39
40 Glossary:
41 * element: a single scalar value that is an element of a SIMD vector.
42 it has a width in bits. Every element is made of 1 or
43 more parts.
44 * ElWid: the element-width (really the element type) of an instruction.
45 Either an integer or a FP type. Integer `ElWid`s are sign-agnostic.
46 In Python, `ElWid` is either an enum type or is `int`.
47 Example `ElWid` definition for integers:
48
49 class ElWid(Enum):
50 I64 = ... # SVP64 value 0b00
51 I32 = ... # SVP64 value 0b01
52 I16 = ... # SVP64 value 0b10
53 I8 = ... # SVP64 value 0b11
54
55 Example `ElWid` definition for floats:
56
57 class ElWid(Enum):
58 F64 = ... # SVP64 value 0b00
59 F32 = ... # SVP64 value 0b01
60 F16 = ... # SVP64 value 0b10
61 BF16 = ... # SVP64 value 0b11
62
63 * elwid: ElWid or nmigen Value with ElWid as the shape
64 the current element-width
65
66 * vec_el_counts: dict[ElWid, int]
67 a map from `ElWid` values `k` to the number of vector elements
68 required within a partition when `elwid == k`.
69
70 Example:
71 vec_el_counts = {ElWid.I8(==0b11): 8, # 8 vector elements
72 ElWid.I16(==0b10): 4, # 4 vector elements
73 ElWid.I32(==0b01): 2, # 2 vector elements
74 ElWid.I64(==0b00): 1} # 1 vector (aka scalar) element
75
76 Another Example:
77 vec_el_counts = {ElWid.BF16(==0b11): 4, # 4 vector elements
78 ElWid.F16(==0b10): 4, # 4 vector elements
79 ElWid.F32(==0b01): 2, # 2 vector elements
80 ElWid.F64(==0b00): 1} # 1 (aka scalar) vector element
81
82 * lane_shapes: int or Mapping[ElWid, int] (optional)
83 the bit-width of all elements in a SIMD layout.
84 if not provided, the lane_shapes are computed from fixed_width
85 and vec_el_counts at each elwidth.
86
87 * fixed_width: int (optional)
88 the total width of a SIMD vector. One or both of lane_shapes or
89 fixed_width may be provided. Both may not be left out.
90 """
91 # when there are no lane_shapes specified, this indicates a
92 # desire to use the maximum available space based on the fixed width
93 # https://bugs.libre-soc.org/show_bug.cgi?id=713#c67
94 if lane_shapes is None:
95 assert fixed_width is not None, \
96 "both fixed_width and lane_shapes cannot be None"
97 lane_shapes = {i: fixed_width // vec_el_counts[i]
98 for i in vec_el_counts}
99 print("lane_shapes", fixed_width, lane_shapes)
100
101 # identify if the lane_shapes is a mapping (dict, etc.)
102 # if not, then assume that it is an integer (width) that
103 # needs to be requested across all partitions
104 if not isinstance(lane_shapes, Mapping):
105 lane_shapes = {i: lane_shapes for i in vec_el_counts}
106
107 # compute a set of partition widths
108 print("lane_shapes", lane_shapes, "vec_el_counts", vec_el_counts)
109 cpart_wid = 0
110 width = 0
111 for i, lwid in lane_shapes.items():
112 required_width = lwid * vec_el_counts[i]
113 print(" required width", cpart_wid, i, lwid, required_width)
114 if required_width > width:
115 cpart_wid = lwid
116 width = required_width
117
118 # calculate the minumum width required if fixed_width specified
119 part_count = max(vec_el_counts.values())
120 print("width", width, cpart_wid, part_count)
121 if fixed_width is not None: # override the width and part_wid
122 assert width <= fixed_width, "not enough space to fit partitions"
123 part_wid = fixed_width // part_count
124 assert part_wid * part_count == fixed_width, \
125 "calculated width not aligned multiples"
126 width = fixed_width
127 print("part_wid", part_wid, "count", part_count, "width", width)
128
129 # create the breakpoints dictionary.
130 # do multi-stage version https://bugs.libre-soc.org/show_bug.cgi?id=713#c34
131 # https://stackoverflow.com/questions/26367812/
132 dpoints = defaultdict(list) # if empty key, create a (empty) list
133 for i, c in vec_el_counts.items():
134 print("dpoints", i, "count", c)
135 # calculate part_wid based on overall width divided by number
136 # of elements.
137 part_wid = width // c
138
139 def add_p(msg, start, p):
140 print(" adding dpoint", msg, start, part_wid, i, c, p)
141 dpoints[p].append(i) # auto-creates list if key non-existent
142 # for each elwidth, create the required number of vector elements
143 for start in range(c):
144 add_p("start", start, start * part_wid) # start of lane
145 add_p("end ", start, start * part_wid +
146 lane_shapes[i]) # end lane
147
148 # deduplicate dpoints lists
149 for k in dpoints.keys():
150 dpoints[k] = list({i: None for i in dpoints[k]}.keys())
151
152 # do not need the breakpoints at the very start or the very end
153 dpoints.pop(0, None)
154 dpoints.pop(width, None)
155 plist = list(dpoints.keys())
156 plist.sort()
157 print("dpoints")
158 pprint(dict(dpoints))
159
160 # second stage, add (map to) the elwidth==i expressions.
161 # TODO: use nmutil.treereduce?
162 points = {}
163 for p in plist:
164 points[p] = map(lambda i: elwid == i, dpoints[p])
165 points[p] = reduce(operator.or_, points[p])
166
167 # third stage, create the binary values which *if* elwidth is set to i
168 # *would* result in the mask at that elwidth being set to this value
169 # these can easily be double-checked through Assertion
170 bitp = {}
171 for i in vec_el_counts.keys():
172 bitp[i] = 0
173 for p, elwidths in dpoints.items():
174 if i in elwidths:
175 bitpos = plist.index(p)
176 bitp[i] |= 1 << bitpos
177
178 # fourth stage: determine which partitions are 100% unused.
179 # these can then be "blanked out"
180 bmask = (1 << len(plist))-1
181 for p in bitp.values():
182 bmask &= ~p
183 return (PartitionPoints(points), bitp, bmask, width, lane_shapes,
184 part_wid)
185
186
187 if __name__ == '__main__':
188
189 # for each element-width (elwidth 0-3) the number of Vector Elements is:
190 # elwidth=0b00 QTY 1 partitions: | ? |
191 # elwidth=0b01 QTY 1 partitions: | ? |
192 # elwidth=0b10 QTY 2 partitions: | ? | ? |
193 # elwidth=0b11 QTY 4 partitions: | ? | ? | ? | ? |
194 # actual widths of Signals *within* those partitions is given separately
195 vec_el_counts = {
196 0: 1,
197 1: 1,
198 2: 2,
199 3: 4,
200 }
201
202 # width=3 indicates "same width Vector Elements (3) at all elwidths"
203 # elwidth=0b00 1x 5-bit | unused xx ..3 |
204 # elwidth=0b01 1x 6-bit | unused xx ..3 |
205 # elwidth=0b10 2x 12-bit | xxx ..3 | xxx ..3 |
206 # elwidth=0b11 3x 24-bit | ..3| ..3 | ..3 |..3 |
207 # expected partitions (^) | | | (^)
208 # to be at these points: (|) | | | |
209 width_in_all_parts = 3
210
211 for i in range(4):
212 pprint((i, layout(i, vec_el_counts, width_in_all_parts)))
213
214 # specify that the Vector Element lengths are to be *different* at
215 # each of the elwidths.
216 # combined with vec_el_counts we have:
217 # elwidth=0b00 1x 5-bit |<----unused---------->....5|
218 # elwidth=0b01 1x 6-bit |<----unused--------->.....6|
219 # elwidth=0b10 2x 6-bit |unused>.....6|unused>.....6|
220 # elwidth=0b11 4x 6-bit |.....6|.....6|.....6|.....6|
221 # expected partitions (^) ^ ^ ^^ (^)
222 # to be at these points: (|) | | || (|)
223 # (24) 18 12 65 (0)
224 widths_at_elwidth = {
225 0: 5,
226 1: 6,
227 2: 6,
228 3: 6
229 }
230
231 print("5,6,6,6 elements", widths_at_elwidth)
232 for i in range(4):
233 pp, bitp, bm, b, c, d = \
234 layout(i, vec_el_counts, widths_at_elwidth)
235 pprint((i, (pp, bitp, bm, b, c, d)))
236 # now check that the expected partition points occur
237 print("5,6,6,6 ppt keys", pp.keys())
238 assert list(pp.keys()) == [5, 6, 12, 18]
239
240 # this example was probably what the 5,6,6,6 one was supposed to be.
241 # combined with vec_el_counts {0:1, 1:1, 2:2, 3:4} we have:
242 # elwidth=0b00 1x 24-bit |.........................24|
243 # elwidth=0b01 1x 12-bit |<--unused--->|...........12|
244 # elwidth=0b10 2x 5 -bit |unused>|....5|unused>|....5|
245 # elwidth=0b11 4x 6 -bit |.....6|.....6|.....6|.....6|
246 # expected partitions (^) ^^ ^ ^^ (^)
247 # to be at these points: (|) || | || (|)
248 # (24) 1817 12 65 (0)
249 widths_at_elwidth = {
250 0: 24, # QTY 1x 24
251 1: 12, # QTY 1x 12
252 2: 5, # QTY 2x 5
253 3: 6 # QTY 4x 6
254 }
255
256 print("24,12,5,6 elements", widths_at_elwidth)
257 for i in range(4):
258 pp, bitp, bm, b, c, d = \
259 layout(i, vec_el_counts, widths_at_elwidth)
260 pprint((i, (pp, bitp, bm, b, c, d)))
261 # now check that the expected partition points occur
262 print("24,12,5,6 ppt keys", pp.keys())
263 assert list(pp.keys()) == [5, 6, 12, 17, 18]
264
265 # this tests elwidth as an actual Signal. layout is allowed to
266 # determine arbitrarily the overall length
267 # https://bugs.libre-soc.org/show_bug.cgi?id=713#c30
268
269 elwid = Signal(2)
270 pp, bitp, bm, b, c, d = layout(
271 elwid, vec_el_counts, widths_at_elwidth)
272 pprint((pp, b, c, d))
273 for k, v in bitp.items():
274 print("bitp elwidth=%d" % k, bin(v))
275 print("bmask", bin(bm))
276
277 m = Module()
278
279 def process():
280 for i in range(4):
281 yield elwid.eq(i)
282 yield Settle()
283 ppt = []
284 for pval in list(pp.values()):
285 val = yield pval # get nmigen to evaluate pp
286 ppt.append(val)
287 pprint((i, (ppt, b, c, d)))
288 # check the results against bitp static-expected partition points
289 # https://bugs.libre-soc.org/show_bug.cgi?id=713#c47
290 # https://stackoverflow.com/a/27165694
291 ival = int(''.join(map(str, ppt[::-1])), 2)
292 assert ival == bitp[i]
293
294 sim = Simulator(m)
295 sim.add_process(process)
296 sim.run()
297
298 # this tests elwidth as an actual Signal. layout is *not* allowed to
299 # determine arbitrarily the overall length, it is fixed to 64
300 # https://bugs.libre-soc.org/show_bug.cgi?id=713#c22
301
302 elwid = Signal(2)
303 pp, bitp, bm, b, c, d = layout(elwid, vec_el_counts,
304 widths_at_elwidth,
305 fixed_width=64)
306 pprint((pp, b, c, d))
307 for k, v in bitp.items():
308 print("bitp elwidth=%d" % k, bin(v))
309 print("bmask", bin(bm))
310
311 m = Module()
312
313 def process():
314 for i in range(4):
315 yield elwid.eq(i)
316 yield Settle()
317 ppt = []
318 for pval in list(pp.values()):
319 val = yield pval # get nmigen to evaluate pp
320 ppt.append(val)
321 print("test elwidth=%d" % i)
322 pprint((i, (ppt, b, c, d)))
323 # check the results against bitp static-expected partition points
324 # https://bugs.libre-soc.org/show_bug.cgi?id=713#c47
325 # https://stackoverflow.com/a/27165694
326 ival = int(''.join(map(str, ppt[::-1])), 2)
327 assert ival == bitp[i], "ival %s actual %s" % (bin(ival),
328 bin(bitp[i]))
329
330 sim = Simulator(m)
331 sim.add_process(process)
332 sim.run()
333
334 # fixed_width=32 and no lane_widths says "allocate maximum"
335 # i.e. Vector Element Widths are auto-allocated
336 # elwidth=0b00 1x 32-bit | .................32 |
337 # elwidth=0b01 1x 32-bit | .................32 |
338 # elwidth=0b10 2x 12-bit | ......16 | ......16 |
339 # elwidth=0b11 3x 24-bit | ..8| ..8 | ..8 |..8 |
340 # expected partitions (^) | | | (^)
341 # to be at these points: (|) | | | |
342
343 # TODO, fix this so that it is correct. put it at the end so it
344 # shows that things break and doesn't stop the other tests.
345 print("maximum allocation from fixed_width=32")
346 for i in range(4):
347 pprint((i, layout(i, vec_el_counts, fixed_width=32)))
348
349 # example "exponent"
350 # https://libre-soc.org/3d_gpu/architecture/dynamic_simd/shape/
351 # 1xFP64: 11 bits, one exponent
352 # 2xFP32: 8 bits, two exponents
353 # 4xFP16: 5 bits, four exponents
354 # 4xBF16: 8 bits, four exponents
355 vec_el_counts = {
356 0: 1, # QTY 1x FP64
357 1: 2, # QTY 2x FP32
358 2: 4, # QTY 4x FP16
359 3: 4, # QTY 4x BF16
360 }
361 widths_at_elwidth = {
362 0: 11, # FP64 ew=0b00
363 1: 8, # FP32 ew=0b01
364 2: 5, # FP16 ew=0b10
365 3: 8 # BF16 ew=0b11
366 }
367
368 # expected results:
369 #
370 # |31| | |24| 16|15 | | 8|7 0 |
371 # |31|28|26|24| |20|16| 12| |10|8|5|4 0 |
372 # 32bit | x| x| x| | x| x| x|10 .... 0 |
373 # 16bit | x| x|26 ... 16 | x| x|10 .... 0 |
374 # 8bit | x|28 .. 24| 20.16| x|11 .. 8|x|4.. 0 |
375 # unused x x
376
377 print("11,8,5,8 elements (FP64/32/16/BF exponents)", widths_at_elwidth)
378 for i in range(4):
379 pp, bitp, bm, b, c, d = \
380 layout(i, vec_el_counts, widths_at_elwidth,
381 fixed_width=32)
382 pprint((i, (pp, bitp, bin(bm), b, c, d)))
383 # now check that the expected partition points occur
384 print("11,8,5,8 pp keys", pp.keys())
385 #assert list(pp.keys()) == [5,6,12,18]
386
387 ###### ######
388 ###### 2nd test, different from the above, elwid=0b10 ==> 11 bit ######
389 ###### ######
390
391 # example "exponent"
392 vec_el_counts = {
393 0: 1, # QTY 1x FP64
394 1: 2, # QTY 2x FP32
395 2: 4, # QTY 4x FP16
396 3: 4, # QTY 4x BF16
397 }
398 widths_at_elwidth = {
399 0: 11, # FP64 ew=0b00
400 1: 11, # FP32 ew=0b01
401 2: 5, # FP16 ew=0b10
402 3: 8 # BF16 ew=0b11
403 }
404
405 # expected results:
406 #
407 # |31| | |24| 16|15 | | 8|7 0 |
408 # |31|28|26|24| |20|16| 12| |10|8|5|4 0 |
409 # 32bit | x| x| x| | x| x| x|10 .... 0 |
410 # 16bit | x| x|26 ... 16 | x| x|10 .... 0 |
411 # 8bit | x|28 .. 24| 20.16| x|11 .. 8|x|4.. 0 |
412 # unused x x
413
414 print("11,8,5,8 elements (FP64/32/16/BF exponents)", widths_at_elwidth)
415 for i in range(4):
416 pp, bitp, bm, b, c, d = \
417 layout(i, vec_el_counts, widths_at_elwidth,
418 fixed_width=32)
419 pprint((i, (pp, bitp, bin(bm), b, c, d)))
420 # now check that the expected partition points occur
421 print("11,8,5,8 pp keys", pp.keys())
422 #assert list(pp.keys()) == [5,6,12,18]