1 # SPDX-License-Identifier: LGPL-2.1-or-later
2 # See Notices.txt for copyright information
5 Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
7 dynamically-partitionable "all" class, directly equivalent
8 to Signal.allb() except SIMD-partitionable
12 * http://libre-riscv.org/3d_gpu/architecture/dynamic_simd/logicops
13 * http://bugs.libre-riscv.org/show_bug.cgi?id=176
16 from nmigen
import Signal
, Module
, Elaboratable
, Cat
, C
17 from nmigen
.back
.pysim
import Simulator
, Settle
18 from nmigen
.cli
import rtlil
19 from nmutil
.ripple
import RippleLSB
21 from ieee754
.part_mul_add
.partpoints
import PartitionPoints
22 from ieee754
.part_cmp
.experiments
.eq_combiner
import AllCombiner
23 from ieee754
.part_bits
.base
import PartitionedBase
27 class PartitionedAll(PartitionedBase
):
29 def __init__(self
, width
, partition_points
):
30 """Create a ``PartitionedAll`` operator
32 super().__init
__(width
, partition_points
, AllCombiner
, "all")
35 if __name__
== "__main__":
37 from ieee754
.part_mul_add
.partpoints
import make_partition
40 m
.submodules
.allb
= allb
= PartitionedAll(16, make_partition(mask
, 16))
42 vl
= rtlil
.convert(allb
, ports
=allb
.ports())
43 with
open("part_allb.il", "w") as f
:
50 yield allb
.a
.eq(0x8c14)
52 out
= yield allb
.output
54 print("out", bin(out
), "mask", bin(m
))
57 out
= yield allb
.output
59 print("out", bin(out
), "mask", bin(m
))
62 out
= yield allb
.output
64 print("out", bin(out
), "mask", bin(m
))
66 sim
.add_process(process
)
67 with sim
.write_vcd("part_allb.vcd", "part_allb.gtkw", traces
=allb
.ports()):