src/ieee754/part_bits/xor.py

   1 # SPDX-License-Identifier: LGPL-2.1-or-later
   2 # See Notices.txt for copyright information
   3
   4 """
   5 Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   6
   7 dynamically-partitionable "xor" class, directly equivalent
   8 to Signal.xor() except SIMD-partitionable
   9
  10 See:
  11
  12 * http://libre-riscv.org/3d_gpu/architecture/dynamic_simd/logicops
  13 * http://bugs.libre-riscv.org/show_bug.cgi?id=176
  14 """
  15
  16 from nmigen import Signal, Module, Elaboratable, Cat, C
  17 from nmigen.back.pysim import Simulator, Settle
  18 from nmigen.cli import rtlil
  19 from nmutil.ripple import RippleLSB
  20
  21 from ieee754.part_mul_add.partpoints import PartitionPoints
  22 from ieee754.part_cmp.experiments.eq_combiner import XORCombiner
  23 from ieee754.part_bits.base import PartitionedBase
  24
  25
  26
  27 class PartitionedXOR(PartitionedBase):
  28
  29     def __init__(self, width, partition_points):
  30         """Create a ``PartitionedXOR`` operator
  31         """
  32         super().__init__(width, partition_points, XORCombiner, "xor")
  33
  34
  35 if __name__ == "__main__":
  36
  37     from ieee754.part_mul_add.partpoints import make_partition
  38     m = Module()
  39     mask = Signal(4)
  40     m.submodules.xor = xor = PartitionedXOR(16, make_partition(mask, 16))
  41
  42     vl = rtlil.convert(xor, ports=xor.ports())
  43     with open("part_xor.il", "w") as f:
  44         f.write(vl)
  45
  46     sim = Simulator(m)
  47
  48     def process():
  49         yield mask.eq(0b010)
  50         yield xor.a.eq(0x8c14)
  51         yield Settle()
  52         out = yield xor.output
  53         m = yield mask
  54         print("out", bin(out), "mask", bin(m))
  55         yield mask.eq(0b111)
  56         yield Settle()
  57         out = yield xor.output
  58         m = yield mask
  59         print("out", bin(out), "mask", bin(m))
  60         yield mask.eq(0b010)
  61         yield Settle()
  62         out = yield xor.output
  63         m = yield mask
  64         print("out", bin(out), "mask", bin(m))
  65
  66     sim.add_process(process)
  67     with sim.write_vcd("part_xor.vcd", "part_xor.gtkw", traces=xor.ports()):
  68         sim.run()
  69