1 from ieee754
.part_mul_add
.partpoints
import PartitionPoints
2 import ieee754
.part_cmp
.equal_ortree
as ortree
3 import ieee754
.part_cmp
.equal
as equal
4 from nmigen
.cli
import rtlil
5 from nmigen
import Signal
, Module
7 def create_ilang(mod
, name
, ports
):
8 vl
= rtlil
.convert(mod
, ports
=ports
)
9 with
open(name
, "w") as f
:
12 def create_ortree(width
, points
):
13 sig
= Signal(len(points
.values()))
14 for i
, key
in enumerate(points
):
16 eq
= ortree
.PartitionedEq(width
, points
)
18 create_ilang(eq
, "ortree.il", [eq
.a
, eq
.b
, eq
.output
, sig
])
20 def create_equal(width
, points
):
21 sig
= Signal(len(points
.values()))
22 for i
, key
in enumerate(points
):
25 eq
= equal
.PartitionedEq(width
, points
)
27 create_ilang(eq
, "equal.il", [eq
.a
, eq
.b
, eq
.output
, sig
])
30 if __name__
== "__main__":
31 points
= PartitionPoints()
33 for i
in range(sig
.width
):
36 # create_equal(32, points)
37 create_ortree(64, points
)
44 # === design hierarchy ===
52 # Number of wire bits: 89
53 # Number of public wires: 36
54 # Number of public wire bits: 76
55 # Number of memories: 0
56 # Number of memory bits: 0
57 # Number of processes: 0
69 # Number of wires: 121
70 # Number of wire bits: 161
71 # Number of public wires: 12
72 # Number of public wire bits: 52
73 # Number of memories: 0
74 # Number of memory bits: 0
75 # Number of processes: 0
76 # Number of cells: 113