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[ieee754fpu.git] / src / ieee754 / part_cmp / experiments / test.py
1 from ieee754.part_mul_add.partpoints import PartitionPoints
2 import ieee754.part_cmp.equal_ortree as ortree
3 import ieee754.part_cmp.equal as equal
4 from nmigen.cli import rtlil
5 from nmigen import Signal, Module
6
7 def create_ilang(mod, name, ports):
8 vl = rtlil.convert(mod, ports=ports)
9 with open(name, "w") as f:
10 f.write(vl)
11
12 def create_ortree(width, points):
13 sig = Signal(len(points.values()))
14 for i, key in enumerate(points):
15 points[key] = sig[i]
16 eq = ortree.PartitionedEq(width, points)
17
18 create_ilang(eq, "ortree.il", [eq.a, eq.b, eq.output, sig])
19
20 def create_equal(width, points):
21 sig = Signal(len(points.values()))
22 for i, key in enumerate(points):
23 points[key] = sig[i]
24
25 eq = equal.PartitionedEq(width, points)
26
27 create_ilang(eq, "equal.il", [eq.a, eq.b, eq.output, sig])
28
29
30 if __name__ == "__main__":
31 points = PartitionPoints()
32 sig = Signal(7)
33 for i in range(sig.width):
34 points[i*8+8] = True
35
36 # create_equal(32, points)
37 create_ortree(64, points)
38
39
40
41
42
43 # ortree:
44 # === design hierarchy ===
45
46 # top 1
47 # mux1 1
48 # mux2 1
49 # mux3 1
50
51 # Number of wires: 49
52 # Number of wire bits: 89
53 # Number of public wires: 36
54 # Number of public wire bits: 76
55 # Number of memories: 0
56 # Number of memory bits: 0
57 # Number of processes: 0
58 # Number of cells: 29
59 # $_MUX_ 6
60 # $_NOR_ 1
61 # $_NOT_ 3
62 # $_OR_ 8
63 # $_XOR_ 11
64
65
66 # equals:
67 # === top ===
68
69 # Number of wires: 121
70 # Number of wire bits: 161
71 # Number of public wires: 12
72 # Number of public wire bits: 52
73 # Number of memories: 0
74 # Number of memory bits: 0
75 # Number of processes: 0
76 # Number of cells: 113
77 # $_ANDNOT_ 32
78 # $_AND_ 7
79 # $_MUX_ 4
80 # $_NAND_ 1
81 # $_NOR_ 2
82 # $_NOT_ 1
83 # $_ORNOT_ 6
84 # $_OR_ 44
85 # $_XNOR_ 1
86 # $_XOR_ 15