1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Signal
, Module
, Elaboratable
11 initial begin q=1'b0; q1=1'b1; end
15 {1'b0,1'b0}:begin q=q; q1=q1; end
16 {1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
17 {1'b1,1'b0}:begin q=1'b1; q1=1'b0; end
18 {1'b1,1'b1}: begin q=~q; q1=~q1; end
24 class SRLatch(Elaboratable
):
25 def __init__(self
, sync
=True):
27 self
.s
= Signal(reset_less
=True)
28 self
.r
= Signal(reset_less
=True)
29 self
.q
= Signal(reset_less
=True)
30 self
.qn
= Signal(reset_less
=True)
32 def elaborate(self
, platform
):
34 q_int
= Signal(reset_less
=True)
38 m
.d
.sync
+= q_int
.eq(1)
40 m
.d
.sync
+= q_int
.eq(0)
42 m
.d
.sync
+= q_int
.eq(q_int
)
43 m
.d
.comb
+= self
.q
.eq(q_int
)
46 m
.d
.sync
+= q_int
.eq(1)
47 m
.d
.comb
+= self
.q
.eq(1)
49 m
.d
.sync
+= q_int
.eq(0)
50 m
.d
.comb
+= self
.q
.eq(0)
52 m
.d
.sync
+= q_int
.eq(q_int
)
53 m
.d
.comb
+= self
.q
.eq(q_int
)
54 m
.d
.comb
+= self
.qn
.eq(~self
.q
)
59 return self
.s
, self
.r
, self
.q
, self
.qn
87 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
88 with
open("test_srlatch.il", "w") as f
:
91 run_simulation(dut
, sr_sim(dut
), vcd_name
='test_srlatch.vcd')
93 dut
= SRLatch(sync
=False)
94 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
95 with
open("test_srlatch_async.il", "w") as f
:
98 run_simulation(dut
, sr_sim(dut
), vcd_name
='test_srlatch_async.vcd')
100 if __name__
== '__main__':