src/scoreboard/fu_fu_matrix.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Elaboratable, Array, Cat, Const
   4
   5 #from nmutil.latch import SRLatch
   6 from .fu_dep_cell import FUDependenceCell
   7 from .fu_picker_vec import FU_Pick_Vec
   8
   9 """
  10
  11  6600 Function Unit Dependency Table Matrix inputs / outputs
  12  -----------------------------------------------------------
  13
  14 """
  15
  16 class FUFUDepMatrix(Elaboratable):
  17     """ implements 11.4.7 mitch alsup FU-to-Reg Dependency Matrix, p26
  18     """
  19     def __init__(self, n_fu_row, n_fu_col):
  20         self.n_fu_row = n_fu_row                  # Y (FU row#)   ^v
  21         self.n_fu_col = n_fu_col                # X (FU col #)  <>
  22         self.rd_pend_i = Signal(n_fu_row, reset_less=True) # Rd pending (left)
  23         self.wr_pend_i = Signal(n_fu_row, reset_less=True) # Wr pending (left)
  24         self.issue_i = Signal(n_fu_col, reset_less=True)    # Issue in (top)
  25
  26         self.go_wr_i = Signal(n_fu_row, reset_less=True) # Go Write in (left)
  27         self.go_rd_i = Signal(n_fu_row, reset_less=True)  # Go Read in (left)
  28         self.go_die_i = Signal(n_fu_row, reset_less=True) # Go Die in (left)
  29
  30         # for Function Unit Readable/Writable (horizontal)
  31         self.readable_o = Signal(n_fu_col, reset_less=True) # readable (bot)
  32         self.writable_o = Signal(n_fu_col, reset_less=True) # writable (bot)
  33
  34     def elaborate(self, platform):
  35         m = Module()
  36
  37         # ---
  38         # matrix of dependency cells
  39         # ---
  40         dm = Array(FUDependenceCell(f, self.n_fu_col) \
  41                                             for f in range(self.n_fu_row))
  42         for y in range(self.n_fu_row):
  43                 setattr(m.submodules, "dm%d" % y, dm[y])
  44
  45         # ---
  46         # array of Function Unit Readable/Writable: row-length, horizontal
  47         # ---
  48         fur = Array(FU_Pick_Vec(self.n_fu_row) for r in range(self.n_fu_col))
  49         for x in range(self.n_fu_col):
  50             setattr(m.submodules, "fur_x%d" % (x), fur[x])
  51
  52         # ---
  53         # connect FU Readable/Writable vector
  54         # ---
  55         readable = []
  56         writable = []
  57         for x in range(self.n_fu_col):
  58             fu = fur[x]
  59             # accumulate Readable/Writable Vector outputs
  60             readable.append(fu.readable_o)
  61             writable.append(fu.writable_o)
  62
  63         # ... and output them from this module (horizontal, width=REGs)
  64         m.d.comb += self.readable_o.eq(Cat(*readable))
  65         m.d.comb += self.writable_o.eq(Cat(*writable))
  66
  67         # ---
  68         # connect FU Pending
  69         # ---
  70         for y in range(self.n_fu_row):
  71             dc = dm[y]
  72             fu = fur[y]
  73             # connect cell reg-select outputs to Reg Vector In
  74             m.d.comb += [fu.rd_pend_i.eq(dc.rd_wait_o),
  75                          fu.wr_pend_i.eq(dc.wr_wait_o),
  76                         ]
  77
  78         # ---
  79         # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
  80         # ---
  81         for x in range(self.n_fu_col):
  82             issue_i = []
  83             for y in range(self.n_fu_row):
  84                 dc = dm[y]
  85                 # accumulate cell inputs issue
  86                 issue_i.append(dc.issue_i[x])
  87             # wire up inputs from module to row cell inputs
  88             m.d.comb += Cat(*issue_i).eq(self.issue_i)
  89
  90         # ---
  91         # connect Matrix go_rd_i/go_wr_i to module readable/writable
  92         # ---
  93         for y in range(self.n_fu_row):
  94             dc = dm[y]
  95             # wire up inputs from module to row cell inputs
  96             m.d.comb += [dc.go_rd_i.eq(self.go_rd_i),
  97                          dc.go_wr_i.eq(self.go_wr_i),
  98                          dc.go_die_i.eq(self.go_die_i),
  99                         ]
 100
 101         # ---
 102         # connect Matrix pending
 103         # ---
 104         for y in range(self.n_fu_row):
 105             dc = dm[y]
 106             # wire up inputs from module to row cell inputs
 107             m.d.comb += [dc.rd_pend_i.eq(self.rd_pend_i),
 108                          dc.wr_pend_i.eq(self.wr_pend_i),
 109                         ]
 110
 111         return m
 112
 113     def __iter__(self):
 114         yield self.rd_pend_i
 115         yield self.wr_pend_i
 116         yield self.issue_i
 117         yield self.go_wr_i
 118         yield self.go_rd_i
 119         yield self.readable_o
 120         yield self.writable_o
 121
 122     def ports(self):
 123         return list(self)
 124
 125 def d_matrix_sim(dut):
 126     """ XXX TODO
 127     """
 128     yield dut.dest_i.eq(1)
 129     yield dut.issue_i.eq(1)
 130     yield
 131     yield dut.issue_i.eq(0)
 132     yield
 133     yield dut.src1_i.eq(1)
 134     yield dut.issue_i.eq(1)
 135     yield
 136     yield dut.issue_i.eq(0)
 137     yield
 138     yield dut.go_rd_i.eq(1)
 139     yield
 140     yield dut.go_rd_i.eq(0)
 141     yield
 142     yield dut.go_wr_i.eq(1)
 143     yield
 144     yield dut.go_wr_i.eq(0)
 145     yield
 146
 147 def test_fu_fu_matrix():
 148     dut = FUFUDepMatrix(n_fu_row=3, n_fu_col=4)
 149     vl = rtlil.convert(dut, ports=dut.ports())
 150     with open("test_fu_fu_matrix.il", "w") as f:
 151         f.write(vl)
 152
 153     run_simulation(dut, d_matrix_sim(dut), vcd_name='test_fu_fu_matrix.vcd')
 154
 155 if __name__ == '__main__':
 156     test_fu_fu_matrix()