src/scoreboard/fu_fu_matrix.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Elaboratable, Array, Cat, Const
   4
   5 from .fu_dep_cell import FUDependenceCell
   6 from .fu_picker_vec import FU_Pick_Vec
   7
   8 """
   9
  10  6600 Function Unit Dependency Table Matrix inputs / outputs
  11  -----------------------------------------------------------
  12
  13 """
  14
  15 class FUFUDepMatrix(Elaboratable):
  16     """ implements 11.4.7 mitch alsup FU-to-Reg Dependency Matrix, p26
  17     """
  18     def __init__(self, n_fu_row, n_fu_col):
  19         self.n_fu_row = n_fu_row                  # Y (FU row#)   ^v
  20         self.n_fu_col = n_fu_col                # X (FU col #)  <>
  21         self.rd_pend_i = Signal(n_fu_row, reset_less=True) # Rd pending (left)
  22         self.wr_pend_i = Signal(n_fu_row, reset_less=True) # Wr pending (left)
  23         self.issue_i = Signal(n_fu_col, reset_less=True)    # Issue in (top)
  24
  25         self.go_wr_i = Signal(n_fu_row, reset_less=True) # Go Write in (left)
  26         self.go_rd_i = Signal(n_fu_row, reset_less=True)  # Go Read in (left)
  27         self.go_die_i = Signal(n_fu_row, reset_less=True) # Go Die in (left)
  28
  29         # for Function Unit Readable/Writable (horizontal)
  30         self.readable_o = Signal(n_fu_col, reset_less=True) # readable (bot)
  31         self.writable_o = Signal(n_fu_col, reset_less=True) # writable (bot)
  32
  33     def elaborate(self, platform):
  34         m = Module()
  35
  36         # ---
  37         # matrix of dependency cells
  38         # ---
  39         dm = Array(FUDependenceCell(f, self.n_fu_col) \
  40                                             for f in range(self.n_fu_row))
  41         for y in range(self.n_fu_row):
  42                 setattr(m.submodules, "dm%d" % y, dm[y])
  43
  44         # ---
  45         # array of Function Unit Readable/Writable: row-length, horizontal
  46         # ---
  47         fur = Array(FU_Pick_Vec(self.n_fu_row) for r in range(self.n_fu_col))
  48         for x in range(self.n_fu_col):
  49             setattr(m.submodules, "fur_x%d" % (x), fur[x])
  50
  51         # ---
  52         # connect FU Readable/Writable vector
  53         # ---
  54         readable = []
  55         writable = []
  56         for y in range(self.n_fu_row):
  57             fu = fur[y]
  58             # accumulate Readable/Writable Vector outputs
  59             readable.append(fu.readable_o)
  60             writable.append(fu.writable_o)
  61
  62         # ... and output them from this module (horizontal, width=REGs)
  63         m.d.comb += self.readable_o.eq(Cat(*readable))
  64         m.d.comb += self.writable_o.eq(Cat(*writable))
  65
  66         # ---
  67         # connect FU Pending
  68         # ---
  69         for y in range(self.n_fu_row):
  70             dc = dm[y]
  71             fu = fur[y]
  72             # connect cell reg-select outputs to Reg Vector In
  73             m.d.comb += [fu.rd_pend_i.eq(dc.rd_wait_o),
  74                          fu.wr_pend_i.eq(dc.wr_wait_o),
  75                         ]
  76
  77         # ---
  78         # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
  79         # ---
  80         for x in range(self.n_fu_col):
  81             issue_i = []
  82             for y in range(self.n_fu_row):
  83                 dc = dm[y]
  84                 # accumulate cell inputs issue
  85                 issue_i.append(dc.issue_i[x])
  86             # wire up inputs from module to row cell inputs
  87             m.d.comb += Cat(*issue_i).eq(self.issue_i)
  88
  89         # ---
  90         # connect Matrix go_rd_i/go_wr_i to module readable/writable
  91         # ---
  92         for y in range(self.n_fu_row):
  93             dc = dm[y]
  94             # wire up inputs from module to row cell inputs
  95             m.d.comb += [dc.go_rd_i.eq(self.go_rd_i),
  96                          dc.go_wr_i.eq(self.go_wr_i),
  97                          dc.go_die_i.eq(self.go_die_i),
  98                         ]
  99
 100         # ---
 101         # connect Matrix pending
 102         # ---
 103         for y in range(self.n_fu_row):
 104             dc = dm[y]
 105             # wire up inputs from module to row cell inputs
 106             m.d.comb += [dc.rd_pend_i.eq(self.rd_pend_i),
 107                          dc.wr_pend_i.eq(self.wr_pend_i),
 108                         ]
 109
 110         return m
 111
 112     def __iter__(self):
 113         yield self.rd_pend_i
 114         yield self.wr_pend_i
 115         yield self.issue_i
 116         yield self.go_wr_i
 117         yield self.go_rd_i
 118         yield self.readable_o
 119         yield self.writable_o
 120
 121     def ports(self):
 122         return list(self)
 123
 124 def d_matrix_sim(dut):
 125     """ XXX TODO
 126     """
 127     yield dut.dest_i.eq(1)
 128     yield dut.issue_i.eq(1)
 129     yield
 130     yield dut.issue_i.eq(0)
 131     yield
 132     yield dut.src1_i.eq(1)
 133     yield dut.issue_i.eq(1)
 134     yield
 135     yield dut.issue_i.eq(0)
 136     yield
 137     yield dut.go_rd_i.eq(1)
 138     yield
 139     yield dut.go_rd_i.eq(0)
 140     yield
 141     yield dut.go_wr_i.eq(1)
 142     yield
 143     yield dut.go_wr_i.eq(0)
 144     yield
 145
 146 def test_fu_fu_matrix():
 147     dut = FUFUDepMatrix(n_fu_row=3, n_fu_col=4)
 148     vl = rtlil.convert(dut, ports=dut.ports())
 149     with open("test_fu_fu_matrix.il", "w") as f:
 150         f.write(vl)
 151
 152     run_simulation(dut, d_matrix_sim(dut), vcd_name='test_fu_fu_matrix.vcd')
 153
 154 if __name__ == '__main__':
 155     test_fu_fu_matrix()