src/scoreboard/fu_reg_matrix.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Elaboratable, Array, Cat
   4
   5 from scoreboard.dependence_cell import DependencyRow
   6 from scoreboard.fu_wr_pending import FU_RW_Pend
   7 from scoreboard.reg_select import Reg_Rsv
   8 from scoreboard.global_pending import GlobalPending
   9
  10 """
  11
  12  6600 Dependency Table Matrix inputs / outputs
  13  ---------------------------------------------
  14
  15                 d s1 s2 i  d s1 s2 i  d s1 s2 i  d s1 s2 i
  16                 | |   | |  | |   | |  | |   | |  | |   | |
  17                 v v   v v  v v   v v  v v   v v  v v   v v
  18  go_rd/go_wr -> dm-r0-fu0  dm-r1-fu0  dm-r2-fu0  dm-r3-fu0 -> wr/rd-pend
  19  go_rd/go_wr -> dm-r0-fu1  dm-r1-fu1  dm-r2-fu1  dm-r3-fu1 -> wr/rd-pend
  20  go_rd/go_wr -> dm-r0-fu2  dm-r1-fu2  dm-r2-fu2  dm-r3-fu2 -> wr/rd-pend
  21                  |  |  |    |  |  |    |  |  |    |  |  |
  22                  v  v  v    v  v  v    v  v  v    v  v  v
  23                  d  s1 s2   d  s1 s2   d  s1 s2   d  s1 s2
  24                  reg sel    reg sel    reg sel    reg sel
  25
  26 """
  27
  28 class FURegDepMatrix(Elaboratable):
  29     """ implements 11.4.7 mitch alsup FU-to-Reg Dependency Matrix, p26
  30     """
  31     def __init__(self, n_fu_row, n_reg_col):
  32         self.n_fu_row = n_fu_row                  # Y (FUs)   ^v
  33         self.n_reg_col = n_reg_col                # X (Regs)  <>
  34         self.dest_i = Signal(n_reg_col, reset_less=True)     # Dest in (top)
  35         self.src1_i = Signal(n_reg_col, reset_less=True)     # oper1 in (top)
  36         self.src2_i = Signal(n_reg_col, reset_less=True)     # oper2 in (top)
  37
  38         # Register "Global" vectors for determining RaW and WaR hazards
  39         self.wr_pend_i = Signal(n_reg_col, reset_less=True) # wr pending (top)
  40         self.rd_pend_i = Signal(n_reg_col, reset_less=True) # rd pending (top)
  41         self.v_wr_rsel_o = Signal(n_reg_col, reset_less=True) # wr pending (bot)
  42         self.v_rd_rsel_o = Signal(n_reg_col, reset_less=True) # rd pending (bot)
  43
  44         self.issue_i = Signal(n_fu_row, reset_less=True)  # Issue in (top)
  45         self.go_wr_i = Signal(n_fu_row, reset_less=True)  # Go Write in (left)
  46         self.go_rd_i = Signal(n_fu_row, reset_less=True)  # Go Read in (left)
  47         self.go_die_i = Signal(n_fu_row, reset_less=True) # Go Die in (left)
  48
  49         # for Register File Select Lines (horizontal), per-reg
  50         self.dest_rsel_o = Signal(n_reg_col, reset_less=True) # dest reg (bot)
  51         self.src1_rsel_o = Signal(n_reg_col, reset_less=True) # src1 reg (bot)
  52         self.src2_rsel_o = Signal(n_reg_col, reset_less=True) # src2 reg (bot)
  53
  54         # for Function Unit "forward progress" (vertical), per-FU
  55         self.wr_pend_o = Signal(n_fu_row, reset_less=True) # wr pending (right)
  56         self.rd_pend_o = Signal(n_fu_row, reset_less=True) # rd pending (right)
  57         self.rd_src1_pend_o = Signal(n_fu_row, reset_less=True) # src1 pending
  58         self.rd_src2_pend_o = Signal(n_fu_row, reset_less=True) # src2 pending
  59
  60     def elaborate(self, platform):
  61         m = Module()
  62
  63         # ---
  64         # matrix of dependency cells
  65         # ---
  66         dm = Array(DependencyRow(self.n_reg_col, 2) \
  67                     for r in range(self.n_fu_row))
  68         for fu in range(self.n_fu_row):
  69             setattr(m.submodules, "dr_fu%d" % fu, dm[fu])
  70
  71         # ---
  72         # array of Function Unit Pending vectors
  73         # ---
  74         fupend = Array(FU_RW_Pend(self.n_reg_col) for f in range(self.n_fu_row))
  75         for fu in range(self.n_fu_row):
  76             setattr(m.submodules, "fu_fu%d" % (fu), fupend[fu])
  77
  78         # ---
  79         # array of Register Reservation vectors
  80         # ---
  81         regrsv = Array(Reg_Rsv(self.n_fu_row) for r in range(self.n_reg_col))
  82         for rn in range(self.n_reg_col):
  83             setattr(m.submodules, "rr_r%d" % (rn), regrsv[rn])
  84
  85         # ---
  86         # connect Function Unit vector
  87         # ---
  88         wr_pend = []
  89         rd_pend = []
  90         rd_src1_pend = []
  91         rd_src2_pend = []
  92         for fu in range(self.n_fu_row):
  93             dc = dm[fu]
  94             fup = fupend[fu]
  95             dest_fwd_o = []
  96             src1_fwd_o = []
  97             src2_fwd_o = []
  98             for rn in range(self.n_reg_col):
  99                 # accumulate cell fwd outputs for dest/src1/src2
 100                 dest_fwd_o.append(dc.dest_fwd_o[rn])
 101                 src1_fwd_o.append(dc.src_fwd_o[0][rn])
 102                 src2_fwd_o.append(dc.src_fwd_o[1][rn])
 103             # connect cell fwd outputs to FU Vector in [Cat is gooood]
 104             m.d.comb += [fup.dest_fwd_i.eq(Cat(*dest_fwd_o)),
 105                          fup.src1_fwd_i.eq(Cat(*src1_fwd_o)),
 106                          fup.src2_fwd_i.eq(Cat(*src2_fwd_o))
 107                         ]
 108             # accumulate FU Vector outputs
 109             wr_pend.append(fup.reg_wr_pend_o)
 110             rd_pend.append(fup.reg_rd_pend_o)
 111             rd_src1_pend.append(fup.reg_rd_src1_pend_o)
 112             rd_src2_pend.append(fup.reg_rd_src2_pend_o)
 113
 114         # ... and output them from this module (vertical, width=FUs)
 115         m.d.comb += self.wr_pend_o.eq(Cat(*wr_pend))
 116         m.d.comb += self.rd_pend_o.eq(Cat(*rd_pend))
 117         m.d.comb += self.rd_src1_pend_o.eq(Cat(*rd_src1_pend))
 118         m.d.comb += self.rd_src2_pend_o.eq(Cat(*rd_src2_pend))
 119
 120         # ---
 121         # connect Reg Selection vector
 122         # ---
 123         dest_rsel = []
 124         src1_rsel = []
 125         src2_rsel = []
 126         for rn in range(self.n_reg_col):
 127             rsv = regrsv[rn]
 128             dest_rsel_o = []
 129             src1_rsel_o = []
 130             src2_rsel_o = []
 131             for fu in range(self.n_fu_row):
 132                 dc = dm[fu]
 133                 # accumulate cell reg-select outputs dest/src1/src2
 134                 dest_rsel_o.append(dc.dest_rsel_o[rn])
 135                 src1_rsel_o.append(dc.src_rsel_o[0][rn])
 136                 src2_rsel_o.append(dc.src_rsel_o[1][rn])
 137             # connect cell reg-select outputs to Reg Vector In
 138             m.d.comb += [rsv.dest_rsel_i.eq(Cat(*dest_rsel_o)),
 139                          rsv.src1_rsel_i.eq(Cat(*src1_rsel_o)),
 140                          rsv.src2_rsel_i.eq(Cat(*src2_rsel_o)),
 141                         ]
 142             # accumulate Reg-Sel Vector outputs
 143             dest_rsel.append(rsv.dest_rsel_o)
 144             src1_rsel.append(rsv.src1_rsel_o)
 145             src2_rsel.append(rsv.src2_rsel_o)
 146
 147         # ... and output them from this module (horizontal, width=REGs)
 148         m.d.comb += self.dest_rsel_o.eq(Cat(*dest_rsel))
 149         m.d.comb += self.src1_rsel_o.eq(Cat(*src1_rsel))
 150         m.d.comb += self.src2_rsel_o.eq(Cat(*src2_rsel))
 151
 152         # ---
 153         # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
 154         # ---
 155         for fu in range(self.n_fu_row):
 156             dc = dm[fu]
 157             # wire up inputs from module to row cell inputs (Cat is gooood)
 158             m.d.comb += [dc.dest_i.eq(self.dest_i),
 159                          dc.src_i[0].eq(self.src1_i),
 160                          dc.src_i[1].eq(self.src2_i),
 161                          dc.rd_pend_i.eq(self.rd_pend_i),
 162                          dc.wr_pend_i.eq(self.wr_pend_i),
 163                         ]
 164
 165         # accumulate rsel bits into read/write pending vectors.
 166         rd_pend_v = []
 167         wr_pend_v = []
 168         for fu in range(self.n_fu_row):
 169             dc = dm[fu]
 170             rd_pend_v.append(dc.v_rd_rsel_o)
 171             wr_pend_v.append(dc.v_wr_rsel_o)
 172         rd_v = GlobalPending(self.n_reg_col, rd_pend_v)
 173         wr_v = GlobalPending(self.n_reg_col, wr_pend_v)
 174         m.submodules.rd_v = rd_v
 175         m.submodules.wr_v = wr_v
 176
 177         m.d.comb += self.v_rd_rsel_o.eq(rd_v.g_pend_o)
 178         m.d.comb += self.v_wr_rsel_o.eq(wr_v.g_pend_o)
 179
 180         # ---
 181         # connect Dep issue_i/go_rd_i/go_wr_i to module issue_i/go_rd/go_wr
 182         # ---
 183         go_rd_i = []
 184         go_wr_i = []
 185         go_die_i = []
 186         issue_i = []
 187         for fu in range(self.n_fu_row):
 188             dc = dm[fu]
 189             # accumulate cell fwd outputs for dest/src1/src2
 190             go_rd_i.append(dc.go_rd_i)
 191             go_wr_i.append(dc.go_wr_i)
 192             go_die_i.append(dc.go_die_i)
 193             issue_i.append(dc.issue_i)
 194         # wire up inputs from module to row cell inputs (Cat is gooood)
 195         m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i),
 196                      Cat(*go_wr_i).eq(self.go_wr_i),
 197                      Cat(*go_die_i).eq(self.go_die_i),
 198                      Cat(*issue_i).eq(self.issue_i),
 199                     ]
 200
 201         return m
 202
 203     def __iter__(self):
 204         yield self.dest_i
 205         yield self.src1_i
 206         yield self.src2_i
 207         yield self.issue_i
 208         yield self.go_wr_i
 209         yield self.go_rd_i
 210         yield self.go_die_i
 211         yield self.dest_rsel_o
 212         yield self.src1_rsel_o
 213         yield self.src2_rsel_o
 214         yield self.wr_pend_o
 215         yield self.rd_pend_o
 216         yield self.wr_pend_i
 217         yield self.rd_pend_i
 218         yield self.v_wr_rsel_o
 219         yield self.v_rd_rsel_o
 220         yield self.rd_src1_pend_o
 221         yield self.rd_src2_pend_o
 222
 223     def ports(self):
 224         return list(self)
 225
 226 def d_matrix_sim(dut):
 227     """ XXX TODO
 228     """
 229     yield dut.dest_i.eq(1)
 230     yield dut.issue_i.eq(1)
 231     yield
 232     yield dut.issue_i.eq(0)
 233     yield
 234     yield dut.src1_i.eq(1)
 235     yield dut.issue_i.eq(1)
 236     yield
 237     yield dut.issue_i.eq(0)
 238     yield
 239     yield dut.go_rd_i.eq(1)
 240     yield
 241     yield dut.go_rd_i.eq(0)
 242     yield
 243     yield dut.go_wr_i.eq(1)
 244     yield
 245     yield dut.go_wr_i.eq(0)
 246     yield
 247
 248 def test_d_matrix():
 249     dut = FURegDepMatrix(n_fu_row=3, n_reg_col=4)
 250     vl = rtlil.convert(dut, ports=dut.ports())
 251     with open("test_fu_reg_matrix.il", "w") as f:
 252         f.write(vl)
 253
 254     run_simulation(dut, d_matrix_sim(dut), vcd_name='test_fu_reg_matrix.vcd')
 255
 256 if __name__ == '__main__':
 257     test_d_matrix()