src/scoreboard/fu_reg_matrix.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Elaboratable, Array, Cat
   4
   5 #from nmutil.latch import SRLatch
   6 from .dependence_cell import DependenceCell
   7 from .fu_wr_pending import FU_RW_Pend
   8 from .reg_select import Reg_Rsv
   9
  10 """
  11
  12  6600 Dependency Table Matrix inputs / outputs
  13  ---------------------------------------------
  14
  15                 d s1 s2 i  d s1 s2 i  d s1 s2 i  d s1 s2 i
  16                 | |   | |  | |   | |  | |   | |  | |   | |
  17                 v v   v v  v v   v v  v v   v v  v v   v v
  18  go_rd/go_wr -> dm-r0-fu0  dm-r1-fu0  dm-r2-fu0  dm-r3-fu0 -> wr/rd-pend
  19  go_rd/go_wr -> dm-r0-fu1  dm-r1-fu1  dm-r2-fu1  dm-r3-fu1 -> wr/rd-pend
  20  go_rd/go_wr -> dm-r0-fu2  dm-r1-fu2  dm-r2-fu2  dm-r3-fu2 -> wr/rd-pend
  21                  |  |  |    |  |  |    |  |  |    |  |  |
  22                  v  v  v    v  v  v    v  v  v    v  v  v
  23                  d  s1 s2   d  s1 s2   d  s1 s2   d  s1 s2
  24                  reg sel    reg sel    reg sel    reg sel
  25
  26 """
  27
  28 class FURegDepMatrix(Elaboratable):
  29     """ implements 11.4.7 mitch alsup FU-to-Reg Dependency Matrix, p26
  30     """
  31     def __init__(self, n_fu_row, n_reg_col):
  32         self.n_fu_row = n_fu_row                  # Y (FUs)   ^v
  33         self.n_reg_col = n_reg_col                # X (Regs)  <>
  34         self.dest_i = Signal(n_reg_col, reset_less=True)     # Dest in (top)
  35         self.src1_i = Signal(n_reg_col, reset_less=True)     # oper1 in (top)
  36         self.src2_i = Signal(n_reg_col, reset_less=True)     # oper2 in (top)
  37         self.issue_i = Signal(n_reg_col, reset_less=True)    # Issue in (top)
  38
  39         self.go_wr_i = Signal(n_fu_row, reset_less=True) # Go Write in (left)
  40         self.go_rd_i = Signal(n_fu_row, reset_less=True)  # Go Read in (left)
  41
  42         # for Register File Select Lines (horizontal), per-reg
  43         self.dest_rsel_o = Signal(n_reg_col, reset_less=True) # dest reg (bot)
  44         self.src1_rsel_o = Signal(n_reg_col, reset_less=True) # src1 reg (bot)
  45         self.src2_rsel_o = Signal(n_reg_col, reset_less=True) # src2 reg (bot)
  46
  47         # for Function Unit "forward progress" (vertical), per-FU
  48         self.wr_pend_o = Signal(n_fu_row, reset_less=True) # wr pending (right)
  49         self.rd_pend_o = Signal(n_fu_row, reset_less=True) # rd pending (right)
  50         self.rd_src1_pend_o = Signal(n_fu_row, reset_less=True) # src1 pending
  51         self.rd_src2_pend_o = Signal(n_fu_row, reset_less=True) # src2 pending
  52
  53     def elaborate(self, platform):
  54         m = Module()
  55
  56         # ---
  57         # matrix of dependency cells
  58         # ---
  59         dm = Array(Array(DependenceCell() for r in range(self.n_fu_row)) \
  60                                           for f in range(self.n_reg_col))
  61         for rn in range(self.n_reg_col):
  62             for fu in range(self.n_fu_row):
  63                 setattr(m.submodules, "dm_r%d_fu%d" % (rn, fu), dm[rn][fu])
  64
  65         # ---
  66         # array of Function Unit Pending vectors
  67         # ---
  68         fupend = Array(FU_RW_Pend(self.n_reg_col) for f in range(self.n_fu_row))
  69         for fu in range(self.n_fu_row):
  70             setattr(m.submodules, "fu_fu%d" % (fu), fupend[fu])
  71
  72         # ---
  73         # array of Register Reservation vectors
  74         # ---
  75         regrsv = Array(Reg_Rsv(self.n_fu_row) for r in range(self.n_reg_col))
  76         for rn in range(self.n_reg_col):
  77             setattr(m.submodules, "rr_r%d" % (rn), regrsv[rn])
  78
  79         # ---
  80         # connect Function Unit vector
  81         # ---
  82         wr_pend = []
  83         rd_pend = []
  84         rd_src1_pend = []
  85         rd_src2_pend = []
  86         for fu in range(self.n_fu_row):
  87             fup = fupend[fu]
  88             dest_fwd_o = []
  89             src1_fwd_o = []
  90             src2_fwd_o = []
  91             for rn in range(self.n_reg_col):
  92                 dc = dm[rn][fu]
  93                 # accumulate cell fwd outputs for dest/src1/src2
  94                 dest_fwd_o.append(dc.dest_fwd_o)
  95                 src1_fwd_o.append(dc.src1_fwd_o)
  96                 src2_fwd_o.append(dc.src2_fwd_o)
  97             # connect cell fwd outputs to FU Vector in [Cat is gooood]
  98             m.d.comb += [fup.dest_fwd_i.eq(Cat(*dest_fwd_o)),
  99                          fup.src1_fwd_i.eq(Cat(*src1_fwd_o)),
 100                          fup.src2_fwd_i.eq(Cat(*src2_fwd_o))
 101                         ]
 102             # accumulate FU Vector outputs
 103             wr_pend.append(fup.reg_wr_pend_o)
 104             rd_pend.append(fup.reg_rd_pend_o)
 105             rd_src1_pend.append(fup.reg_rd_src1_pend_o)
 106             rd_src2_pend.append(fup.reg_rd_src2_pend_o)
 107
 108         # ... and output them from this module (vertical, width=FUs)
 109         m.d.comb += self.wr_pend_o.eq(Cat(*wr_pend))
 110         m.d.comb += self.rd_pend_o.eq(Cat(*rd_pend))
 111         m.d.comb += self.rd_src1_pend_o.eq(Cat(*rd_src1_pend))
 112         m.d.comb += self.rd_src2_pend_o.eq(Cat(*rd_src2_pend))
 113
 114         # ---
 115         # connect Reg Selection vector
 116         # ---
 117         dest_rsel = []
 118         src1_rsel = []
 119         src2_rsel = []
 120         for rn in range(self.n_reg_col):
 121             rsv = regrsv[rn]
 122             dest_rsel_o = []
 123             src1_rsel_o = []
 124             src2_rsel_o = []
 125             for fu in range(self.n_fu_row):
 126                 dc = dm[rn][fu]
 127                 # accumulate cell reg-select outputs dest/src1/src2
 128                 dest_rsel_o.append(dc.dest_rsel_o)
 129                 src1_rsel_o.append(dc.src1_rsel_o)
 130                 src2_rsel_o.append(dc.src2_rsel_o)
 131             # connect cell reg-select outputs to Reg Vector In
 132             m.d.comb += [rsv.dest_rsel_i.eq(Cat(*dest_rsel_o)),
 133                          rsv.src1_rsel_i.eq(Cat(*src1_rsel_o)),
 134                          rsv.src2_rsel_i.eq(Cat(*src2_rsel_o)),
 135                         ]
 136             # accumulate Reg-Sel Vector outputs
 137             dest_rsel.append(rsv.dest_rsel_o)
 138             src1_rsel.append(rsv.src1_rsel_o)
 139             src2_rsel.append(rsv.src2_rsel_o)
 140
 141         # ... and output them from this module (horizontal, width=REGs)
 142         m.d.comb += self.dest_rsel_o.eq(Cat(*dest_rsel))
 143         m.d.comb += self.src1_rsel_o.eq(Cat(*src1_rsel))
 144         m.d.comb += self.src2_rsel_o.eq(Cat(*src2_rsel))
 145
 146         # ---
 147         # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
 148         # ---
 149         for rn in range(self.n_reg_col):
 150             dest_i = []
 151             src1_i = []
 152             src2_i = []
 153             issue_i = []
 154             for fu in range(self.n_fu_row):
 155                 dc = dm[rn][fu]
 156                 # accumulate cell inputs dest/src1/src2
 157                 dest_i.append(dc.dest_i)
 158                 src1_i.append(dc.src1_i)
 159                 src2_i.append(dc.src2_i)
 160                 issue_i.append(dc.issue_i)
 161             # wire up inputs from module to row cell inputs (Cat is gooood)
 162             m.d.comb += [Cat(*dest_i).eq(self.dest_i),
 163                          Cat(*src1_i).eq(self.src1_i),
 164                          Cat(*src2_i).eq(self.src2_i),
 165                          Cat(*issue_i).eq(self.issue_i),
 166                         ]
 167
 168         # ---
 169         # connect Dependency Matrix go_rd_i/go_wr_i to module go_rd/go_wr
 170         # ---
 171         for fu in range(self.n_fu_row):
 172             go_rd_i = []
 173             go_wr_i = []
 174             for rn in range(self.n_reg_col):
 175                 dc = dm[rn][fu]
 176                 # accumulate cell fwd outputs for dest/src1/src2
 177                 go_rd_i.append(dc.go_rd_i)
 178                 go_wr_i.append(dc.go_wr_i)
 179             # wire up inputs from module to row cell inputs (Cat is gooood)
 180             m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i),
 181                          Cat(*go_wr_i).eq(self.go_wr_i),
 182                         ]
 183
 184         return m
 185
 186     def __iter__(self):
 187         yield self.dest_i
 188         yield self.src1_i
 189         yield self.src2_i
 190         yield self.issue_i
 191         yield self.go_wr_i
 192         yield self.go_rd_i
 193         yield self.dest_rsel_o
 194         yield self.src1_rsel_o
 195         yield self.src2_rsel_o
 196         yield self.wr_pend_o
 197         yield self.rd_pend_o
 198         yield self.rd_src1_pend_o
 199         yield self.rd_src2_pend_o
 200
 201     def ports(self):
 202         return list(self)
 203
 204 def d_matrix_sim(dut):
 205     """ XXX TODO
 206     """
 207     yield dut.dest_i.eq(1)
 208     yield dut.issue_i.eq(1)
 209     yield
 210     yield dut.issue_i.eq(0)
 211     yield
 212     yield dut.src1_i.eq(1)
 213     yield dut.issue_i.eq(1)
 214     yield
 215     yield dut.issue_i.eq(0)
 216     yield
 217     yield dut.go_rd_i.eq(1)
 218     yield
 219     yield dut.go_rd_i.eq(0)
 220     yield
 221     yield dut.go_wr_i.eq(1)
 222     yield
 223     yield dut.go_wr_i.eq(0)
 224     yield
 225
 226 def test_d_matrix():
 227     dut = FURegDepMatrix(n_fu_row=3, n_reg_col=4)
 228     vl = rtlil.convert(dut, ports=dut.ports())
 229     with open("test_fu_reg_matrix.il", "w") as f:
 230         f.write(vl)
 231
 232     run_simulation(dut, d_matrix_sim(dut), vcd_name='test_fu_reg_matrix.vcd')
 233
 234 if __name__ == '__main__':
 235     test_d_matrix()