1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Elaboratable
, Array
, Cat
5 #from nmutil.latch import SRLatch
6 from scoreboard
.dependence_cell
import DependencyRow
7 from scoreboard
.fu_wr_pending
import FU_RW_Pend
8 from scoreboard
.reg_select
import Reg_Rsv
12 6600 Dependency Table Matrix inputs / outputs
13 ---------------------------------------------
15 d s1 s2 i d s1 s2 i d s1 s2 i d s1 s2 i
16 | | | | | | | | | | | | | | | |
17 v v v v v v v v v v v v v v v v
18 go_rd/go_wr -> dm-r0-fu0 dm-r1-fu0 dm-r2-fu0 dm-r3-fu0 -> wr/rd-pend
19 go_rd/go_wr -> dm-r0-fu1 dm-r1-fu1 dm-r2-fu1 dm-r3-fu1 -> wr/rd-pend
20 go_rd/go_wr -> dm-r0-fu2 dm-r1-fu2 dm-r2-fu2 dm-r3-fu2 -> wr/rd-pend
21 | | | | | | | | | | | |
22 v v v v v v v v v v v v
23 d s1 s2 d s1 s2 d s1 s2 d s1 s2
24 reg sel reg sel reg sel reg sel
28 class FURegDepMatrix(Elaboratable
):
29 """ implements 11.4.7 mitch alsup FU-to-Reg Dependency Matrix, p26
31 def __init__(self
, n_fu_row
, n_reg_col
):
32 self
.n_fu_row
= n_fu_row
# Y (FUs) ^v
33 self
.n_reg_col
= n_reg_col
# X (Regs) <>
34 self
.dest_i
= Signal(n_reg_col
, reset_less
=True) # Dest in (top)
35 self
.src1_i
= Signal(n_reg_col
, reset_less
=True) # oper1 in (top)
36 self
.src2_i
= Signal(n_reg_col
, reset_less
=True) # oper2 in (top)
38 # Register "Global" vectors for determining RaW and WaR hazards
39 self
.wr_pend_i
= Signal(n_reg_col
, reset_less
=True) # wr pending (top)
40 self
.rd_pend_i
= Signal(n_reg_col
, reset_less
=True) # rd pending (top)
41 self
.wr_rsel_o
= Signal(n_reg_col
, reset_less
=True) # wr pending (bot)
42 self
.rd_rsel_o
= Signal(n_reg_col
, reset_less
=True) # rd pending (bot)
44 self
.issue_i
= Signal(n_fu_row
, reset_less
=True) # Issue in (top)
45 self
.go_wr_i
= Signal(n_fu_row
, reset_less
=True) # Go Write in (left)
46 self
.go_rd_i
= Signal(n_fu_row
, reset_less
=True) # Go Read in (left)
48 # for Register File Select Lines (horizontal), per-reg
49 self
.dest_rsel_o
= Signal(n_reg_col
, reset_less
=True) # dest reg (bot)
50 self
.src1_rsel_o
= Signal(n_reg_col
, reset_less
=True) # src1 reg (bot)
51 self
.src2_rsel_o
= Signal(n_reg_col
, reset_less
=True) # src2 reg (bot)
53 # for Function Unit "forward progress" (vertical), per-FU
54 self
.wr_pend_o
= Signal(n_fu_row
, reset_less
=True) # wr pending (right)
55 self
.rd_pend_o
= Signal(n_fu_row
, reset_less
=True) # rd pending (right)
56 self
.rd_src1_pend_o
= Signal(n_fu_row
, reset_less
=True) # src1 pending
57 self
.rd_src2_pend_o
= Signal(n_fu_row
, reset_less
=True) # src2 pending
59 def elaborate(self
, platform
):
63 # matrix of dependency cells
65 dm
= Array(DependencyRow(self
.n_reg_col
) for r
in range(self
.n_fu_row
))
66 for fu
in range(self
.n_fu_row
):
67 setattr(m
.submodules
, "dr_fu%d" % fu
, dm
[fu
])
70 # array of Function Unit Pending vectors
72 fupend
= Array(FU_RW_Pend(self
.n_reg_col
) for f
in range(self
.n_fu_row
))
73 for fu
in range(self
.n_fu_row
):
74 setattr(m
.submodules
, "fu_fu%d" % (fu
), fupend
[fu
])
77 # array of Register Reservation vectors
79 regrsv
= Array(Reg_Rsv(self
.n_fu_row
) for r
in range(self
.n_reg_col
))
80 for rn
in range(self
.n_reg_col
):
81 setattr(m
.submodules
, "rr_r%d" % (rn
), regrsv
[rn
])
84 # connect Function Unit vector
90 for fu
in range(self
.n_fu_row
):
96 for rn
in range(self
.n_reg_col
):
97 # accumulate cell fwd outputs for dest/src1/src2
98 dest_fwd_o
.append(dc
.dest_fwd_o
[rn
])
99 src1_fwd_o
.append(dc
.src1_fwd_o
[rn
])
100 src2_fwd_o
.append(dc
.src2_fwd_o
[rn
])
101 # connect cell fwd outputs to FU Vector in [Cat is gooood]
102 m
.d
.comb
+= [fup
.dest_fwd_i
.eq(Cat(*dest_fwd_o
)),
103 fup
.src1_fwd_i
.eq(Cat(*src1_fwd_o
)),
104 fup
.src2_fwd_i
.eq(Cat(*src2_fwd_o
))
106 # accumulate FU Vector outputs
107 wr_pend
.append(fup
.reg_wr_pend_o
)
108 rd_pend
.append(fup
.reg_rd_pend_o
)
109 rd_src1_pend
.append(fup
.reg_rd_src1_pend_o
)
110 rd_src2_pend
.append(fup
.reg_rd_src2_pend_o
)
112 # ... and output them from this module (vertical, width=FUs)
113 m
.d
.comb
+= self
.wr_pend_o
.eq(Cat(*wr_pend
))
114 m
.d
.comb
+= self
.rd_pend_o
.eq(Cat(*rd_pend
))
115 m
.d
.comb
+= self
.rd_src1_pend_o
.eq(Cat(*rd_src1_pend
))
116 m
.d
.comb
+= self
.rd_src2_pend_o
.eq(Cat(*rd_src2_pend
))
118 print ("wr pend len", len(wr_pend
))
121 # connect Reg Selection vector
126 for rn
in range(self
.n_reg_col
):
131 for fu
in range(self
.n_fu_row
):
133 # accumulate cell reg-select outputs dest/src1/src2
134 dest_rsel_o
.append(dc
.dest_rsel_o
[rn
])
135 src1_rsel_o
.append(dc
.src1_rsel_o
[rn
])
136 src2_rsel_o
.append(dc
.src2_rsel_o
[rn
])
137 # connect cell reg-select outputs to Reg Vector In
138 m
.d
.comb
+= [rsv
.dest_rsel_i
.eq(Cat(*dest_rsel_o
)),
139 rsv
.src1_rsel_i
.eq(Cat(*src1_rsel_o
)),
140 rsv
.src2_rsel_i
.eq(Cat(*src2_rsel_o
)),
142 # accumulate Reg-Sel Vector outputs
143 dest_rsel
.append(rsv
.dest_rsel_o
)
144 src1_rsel
.append(rsv
.src1_rsel_o
)
145 src2_rsel
.append(rsv
.src2_rsel_o
)
146 print ("dest_rsel_rsv len", len(rsv
.dest_rsel_o
))
148 # ... and output them from this module (horizontal, width=REGs)
149 m
.d
.comb
+= self
.dest_rsel_o
.eq(Cat(*dest_rsel
))
150 m
.d
.comb
+= self
.src1_rsel_o
.eq(Cat(*src1_rsel
))
151 m
.d
.comb
+= self
.src2_rsel_o
.eq(Cat(*src2_rsel
))
153 print ("dest rsel len", len(dest_rsel
), self
.dest_rsel_o
)
155 # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
157 for fu
in range(self
.n_fu_row
):
159 # wire up inputs from module to row cell inputs (Cat is gooood)
160 m
.d
.comb
+= [dc
.dest_i
.eq(self
.dest_i
),
161 dc
.src1_i
.eq(self
.src1_i
),
162 dc
.src2_i
.eq(self
.src2_i
),
163 dc
.rd_pend_i
.eq(self
.rd_pend_i
),
164 dc
.wr_pend_i
.eq(self
.wr_pend_i
),
167 # accumulate and OR rsel bits (should be done in a separate module)
170 for rn
in range(self
.n_reg_col
):
173 for fu
in range(self
.n_fu_row
):
175 rd_l
.append(dc
.rd_rsel_o
[rn
])
176 wr_l
.append(dc
.wr_rsel_o
[rn
])
177 rd_pend_v
.append(Cat(*rd_l
).bool())
178 wr_pend_v
.append(Cat(*wr_l
).bool())
180 m
.d
.comb
+= self
.rd_rsel_o
.eq(Cat(*rd_pend_v
))
181 m
.d
.comb
+= self
.wr_rsel_o
.eq(Cat(*wr_pend_v
))
184 # connect Dep issue_i/go_rd_i/go_wr_i to module issue_i/go_rd/go_wr
189 for fu
in range(self
.n_fu_row
):
191 # accumulate cell fwd outputs for dest/src1/src2
192 go_rd_i
.append(dc
.go_rd_i
)
193 go_wr_i
.append(dc
.go_wr_i
)
194 issue_i
.append(dc
.issue_i
)
195 # wire up inputs from module to row cell inputs (Cat is gooood)
196 m
.d
.comb
+= [Cat(*go_rd_i
).eq(self
.go_rd_i
),
197 Cat(*go_wr_i
).eq(self
.go_wr_i
),
198 Cat(*issue_i
).eq(self
.issue_i
),
210 yield self
.dest_rsel_o
211 yield self
.src1_rsel_o
212 yield self
.src2_rsel_o
219 yield self
.rd_src1_pend_o
220 yield self
.rd_src2_pend_o
225 def d_matrix_sim(dut
):
228 yield dut
.dest_i
.eq(1)
229 yield dut
.issue_i
.eq(1)
231 yield dut
.issue_i
.eq(0)
233 yield dut
.src1_i
.eq(1)
234 yield dut
.issue_i
.eq(1)
236 yield dut
.issue_i
.eq(0)
238 yield dut
.go_rd_i
.eq(1)
240 yield dut
.go_rd_i
.eq(0)
242 yield dut
.go_wr_i
.eq(1)
244 yield dut
.go_wr_i
.eq(0)
248 dut
= FURegDepMatrix(n_fu_row
=3, n_reg_col
=4)
249 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
250 with
open("test_fu_reg_matrix.il", "w") as f
:
253 run_simulation(dut
, d_matrix_sim(dut
), vcd_name
='test_fu_reg_matrix.vcd')
255 if __name__
== '__main__':