1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Elaboratable
, Array
, Cat
5 #from nmutil.latch import SRLatch
6 from scoreboard
.dependence_cell
import DependencyRow
7 from scoreboard
.fu_wr_pending
import FU_RW_Pend
8 from scoreboard
.reg_select
import Reg_Rsv
12 6600 Dependency Table Matrix inputs / outputs
13 ---------------------------------------------
15 d s1 s2 i d s1 s2 i d s1 s2 i d s1 s2 i
16 | | | | | | | | | | | | | | | |
17 v v v v v v v v v v v v v v v v
18 go_rd/go_wr -> dm-r0-fu0 dm-r1-fu0 dm-r2-fu0 dm-r3-fu0 -> wr/rd-pend
19 go_rd/go_wr -> dm-r0-fu1 dm-r1-fu1 dm-r2-fu1 dm-r3-fu1 -> wr/rd-pend
20 go_rd/go_wr -> dm-r0-fu2 dm-r1-fu2 dm-r2-fu2 dm-r3-fu2 -> wr/rd-pend
21 | | | | | | | | | | | |
22 v v v v v v v v v v v v
23 d s1 s2 d s1 s2 d s1 s2 d s1 s2
24 reg sel reg sel reg sel reg sel
28 class FURegDepMatrix(Elaboratable
):
29 """ implements 11.4.7 mitch alsup FU-to-Reg Dependency Matrix, p26
31 def __init__(self
, n_fu_row
, n_reg_col
):
32 self
.n_fu_row
= n_fu_row
# Y (FUs) ^v
33 self
.n_reg_col
= n_reg_col
# X (Regs) <>
34 self
.dest_i
= Signal(n_reg_col
, reset_less
=True) # Dest in (top)
35 self
.src1_i
= Signal(n_reg_col
, reset_less
=True) # oper1 in (top)
36 self
.src2_i
= Signal(n_reg_col
, reset_less
=True) # oper2 in (top)
38 self
.issue_i
= Signal(n_fu_row
, reset_less
=True) # Issue in (top)
39 self
.go_wr_i
= Signal(n_fu_row
, reset_less
=True) # Go Write in (left)
40 self
.go_rd_i
= Signal(n_fu_row
, reset_less
=True) # Go Read in (left)
42 # for Register File Select Lines (horizontal), per-reg
43 self
.dest_rsel_o
= Signal(n_reg_col
, reset_less
=True) # dest reg (bot)
44 self
.src1_rsel_o
= Signal(n_reg_col
, reset_less
=True) # src1 reg (bot)
45 self
.src2_rsel_o
= Signal(n_reg_col
, reset_less
=True) # src2 reg (bot)
47 # for Function Unit "forward progress" (vertical), per-FU
48 self
.wr_pend_o
= Signal(n_fu_row
, reset_less
=True) # wr pending (right)
49 self
.rd_pend_o
= Signal(n_fu_row
, reset_less
=True) # rd pending (right)
50 self
.rd_src1_pend_o
= Signal(n_fu_row
, reset_less
=True) # src1 pending
51 self
.rd_src2_pend_o
= Signal(n_fu_row
, reset_less
=True) # src2 pending
53 def elaborate(self
, platform
):
57 # matrix of dependency cells
59 dm
= Array(DependencyRow(self
.n_reg_col
) for r
in range(self
.n_fu_row
))
60 for fu
in range(self
.n_fu_row
):
61 setattr(m
.submodules
, "dr_fu%d" % fu
, dm
[fu
])
64 # array of Function Unit Pending vectors
66 fupend
= Array(FU_RW_Pend(self
.n_reg_col
) for f
in range(self
.n_fu_row
))
67 for fu
in range(self
.n_fu_row
):
68 setattr(m
.submodules
, "fu_fu%d" % (fu
), fupend
[fu
])
71 # array of Register Reservation vectors
73 regrsv
= Array(Reg_Rsv(self
.n_fu_row
) for r
in range(self
.n_reg_col
))
74 for rn
in range(self
.n_reg_col
):
75 setattr(m
.submodules
, "rr_r%d" % (rn
), regrsv
[rn
])
78 # connect Function Unit vector
84 for fu
in range(self
.n_fu_row
):
90 for rn
in range(self
.n_reg_col
):
91 # accumulate cell fwd outputs for dest/src1/src2
92 dest_fwd_o
.append(dc
.dest_fwd_o
[rn
])
93 src1_fwd_o
.append(dc
.src1_fwd_o
[rn
])
94 src2_fwd_o
.append(dc
.src2_fwd_o
[rn
])
95 # connect cell fwd outputs to FU Vector in [Cat is gooood]
96 m
.d
.comb
+= [fup
.dest_fwd_i
.eq(Cat(*dest_fwd_o
)),
97 fup
.src1_fwd_i
.eq(Cat(*src1_fwd_o
)),
98 fup
.src2_fwd_i
.eq(Cat(*src2_fwd_o
))
100 # accumulate FU Vector outputs
101 wr_pend
.append(fup
.reg_wr_pend_o
)
102 rd_pend
.append(fup
.reg_rd_pend_o
)
103 rd_src1_pend
.append(fup
.reg_rd_src1_pend_o
)
104 rd_src2_pend
.append(fup
.reg_rd_src2_pend_o
)
106 # ... and output them from this module (vertical, width=FUs)
107 m
.d
.comb
+= self
.wr_pend_o
.eq(Cat(*wr_pend
))
108 m
.d
.comb
+= self
.rd_pend_o
.eq(Cat(*rd_pend
))
109 m
.d
.comb
+= self
.rd_src1_pend_o
.eq(Cat(*rd_src1_pend
))
110 m
.d
.comb
+= self
.rd_src2_pend_o
.eq(Cat(*rd_src2_pend
))
112 print ("wr pend len", len(wr_pend
))
115 # connect Reg Selection vector
120 for rn
in range(self
.n_reg_col
):
125 for fu
in range(self
.n_fu_row
):
127 # accumulate cell reg-select outputs dest/src1/src2
128 dest_rsel_o
.append(dc
.dest_rsel_o
[rn
])
129 src1_rsel_o
.append(dc
.src1_rsel_o
[rn
])
130 src2_rsel_o
.append(dc
.src2_rsel_o
[rn
])
131 # connect cell reg-select outputs to Reg Vector In
132 m
.d
.comb
+= [rsv
.dest_rsel_i
.eq(Cat(*dest_rsel_o
)),
133 rsv
.src1_rsel_i
.eq(Cat(*src1_rsel_o
)),
134 rsv
.src2_rsel_i
.eq(Cat(*src2_rsel_o
)),
136 # accumulate Reg-Sel Vector outputs
137 dest_rsel
.append(rsv
.dest_rsel_o
)
138 src1_rsel
.append(rsv
.src1_rsel_o
)
139 src2_rsel
.append(rsv
.src2_rsel_o
)
140 print ("dest_rsel_rsv len", len(rsv
.dest_rsel_o
))
142 # ... and output them from this module (horizontal, width=REGs)
143 m
.d
.comb
+= self
.dest_rsel_o
.eq(Cat(*dest_rsel
))
144 m
.d
.comb
+= self
.src1_rsel_o
.eq(Cat(*src1_rsel
))
145 m
.d
.comb
+= self
.src2_rsel_o
.eq(Cat(*src2_rsel
))
147 print ("dest rsel len", len(dest_rsel
), self
.dest_rsel_o
)
149 # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
151 for fu
in range(self
.n_fu_row
):
153 # wire up inputs from module to row cell inputs (Cat is gooood)
154 m
.d
.comb
+= [dc
.dest_i
.eq(self
.dest_i
),
155 dc
.src1_i
.eq(self
.src1_i
),
156 dc
.src2_i
.eq(self
.src2_i
),
160 # connect Dep issue_i/go_rd_i/go_wr_i to module issue_i/go_rd/go_wr
165 for fu
in range(self
.n_fu_row
):
167 # accumulate cell fwd outputs for dest/src1/src2
168 go_rd_i
.append(dc
.go_rd_i
)
169 go_wr_i
.append(dc
.go_wr_i
)
170 issue_i
.append(dc
.issue_i
)
171 # wire up inputs from module to row cell inputs (Cat is gooood)
172 m
.d
.comb
+= [Cat(*go_rd_i
).eq(self
.go_rd_i
),
173 Cat(*go_wr_i
).eq(self
.go_wr_i
),
174 Cat(*issue_i
).eq(self
.issue_i
),
186 yield self
.dest_rsel_o
187 yield self
.src1_rsel_o
188 yield self
.src2_rsel_o
191 yield self
.rd_src1_pend_o
192 yield self
.rd_src2_pend_o
197 def d_matrix_sim(dut
):
200 yield dut
.dest_i
.eq(1)
201 yield dut
.issue_i
.eq(1)
203 yield dut
.issue_i
.eq(0)
205 yield dut
.src1_i
.eq(1)
206 yield dut
.issue_i
.eq(1)
208 yield dut
.issue_i
.eq(0)
210 yield dut
.go_rd_i
.eq(1)
212 yield dut
.go_rd_i
.eq(0)
214 yield dut
.go_wr_i
.eq(1)
216 yield dut
.go_wr_i
.eq(0)
220 dut
= FURegDepMatrix(n_fu_row
=3, n_reg_col
=4)
221 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
222 with
open("test_fu_reg_matrix.il", "w") as f
:
225 run_simulation(dut
, d_matrix_sim(dut
), vcd_name
='test_fu_reg_matrix.vcd')
227 if __name__
== '__main__':