src/scoreboard/fu_reg_matrix.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Elaboratable, Array, Cat
   4
   5 from scoreboard.dependence_cell import DependencyRow
   6 from scoreboard.fu_wr_pending import FU_RW_Pend
   7 from scoreboard.reg_select import Reg_Rsv
   8 from scoreboard.global_pending import GlobalPending
   9
  10 """
  11
  12  6600 Dependency Table Matrix inputs / outputs
  13  ---------------------------------------------
  14
  15                 d s1 s2 i  d s1 s2 i  d s1 s2 i  d s1 s2 i
  16                 | |   | |  | |   | |  | |   | |  | |   | |
  17                 v v   v v  v v   v v  v v   v v  v v   v v
  18  go_rd/go_wr -> dm-r0-fu0  dm-r1-fu0  dm-r2-fu0  dm-r3-fu0 -> wr/rd-pend
  19  go_rd/go_wr -> dm-r0-fu1  dm-r1-fu1  dm-r2-fu1  dm-r3-fu1 -> wr/rd-pend
  20  go_rd/go_wr -> dm-r0-fu2  dm-r1-fu2  dm-r2-fu2  dm-r3-fu2 -> wr/rd-pend
  21                  |  |  |    |  |  |    |  |  |    |  |  |
  22                  v  v  v    v  v  v    v  v  v    v  v  v
  23                  d  s1 s2   d  s1 s2   d  s1 s2   d  s1 s2
  24                  reg sel    reg sel    reg sel    reg sel
  25
  26 """
  27
  28 class FURegDepMatrix(Elaboratable):
  29     """ implements 11.4.7 mitch alsup FU-to-Reg Dependency Matrix, p26
  30     """
  31     def __init__(self, n_fu_row, n_reg_col, n_src):
  32         self.n_src = n_src
  33         self.n_fu_row = nf = n_fu_row      # Y (FUs)   ^v
  34         self.n_reg_col = n_reg = n_reg_col   # X (Regs)  <>
  35
  36         # arrays
  37         src = []
  38         rsel = []
  39         for i in range(n_src):
  40             j = i + 1 # name numbering to match src1/src2
  41             src.append(Signal(n_reg, name="src%d" % j, reset_less=True))
  42             rsel.append(Signal(n_reg, name="src%d_rsel_o" % j, reset_less=True))
  43         pend = []
  44         for i in range(nf):
  45             j = i + 1 # name numbering to match src1/src2
  46             pend.append(Signal(nf, name="rd_src%d_pend_o" % j, reset_less=True))
  47
  48         self.dest_i = Signal(n_reg_col, reset_less=True)     # Dest in (top)
  49         self.src_i = Array(src)                              # oper in (top)
  50
  51         # Register "Global" vectors for determining RaW and WaR hazards
  52         self.wr_pend_i = Signal(n_reg_col, reset_less=True) # wr pending (top)
  53         self.rd_pend_i = Signal(n_reg_col, reset_less=True) # rd pending (top)
  54         self.v_wr_rsel_o = Signal(n_reg_col, reset_less=True) # wr pending (bot)
  55         self.v_rd_rsel_o = Signal(n_reg_col, reset_less=True) # rd pending (bot)
  56
  57         self.issue_i = Signal(n_fu_row, reset_less=True)  # Issue in (top)
  58         self.go_wr_i = Signal(n_fu_row, reset_less=True)  # Go Write in (left)
  59         self.go_rd_i = Signal(n_fu_row, reset_less=True)  # Go Read in (left)
  60         self.go_die_i = Signal(n_fu_row, reset_less=True) # Go Die in (left)
  61
  62         # for Register File Select Lines (horizontal), per-reg
  63         self.dest_rsel_o = Signal(n_reg_col, reset_less=True) # dest reg (bot)
  64         self.src_rsel_o = Array(rsel)                         # src reg (bot)
  65
  66         # for Function Unit "forward progress" (vertical), per-FU
  67         self.wr_pend_o = Signal(n_fu_row, reset_less=True) # wr pending (right)
  68         self.rd_pend_o = Signal(n_fu_row, reset_less=True) # rd pending (right)
  69         self.rd_src_pend_o = Array(pend) # src1 pending
  70
  71     def elaborate(self, platform):
  72         m = Module()
  73
  74         # ---
  75         # matrix of dependency cells
  76         # ---
  77         dm = Array(DependencyRow(self.n_reg_col, self.n_src) \
  78                     for r in range(self.n_fu_row))
  79         for fu in range(self.n_fu_row):
  80             setattr(m.submodules, "dr_fu%d" % fu, dm[fu])
  81
  82         # ---
  83         # array of Function Unit Pending vectors
  84         # ---
  85         fupend = Array(FU_RW_Pend(self.n_reg_col, self.n_src) \
  86                         for f in range(self.n_fu_row))
  87         for fu in range(self.n_fu_row):
  88             setattr(m.submodules, "fu_fu%d" % (fu), fupend[fu])
  89
  90         # ---
  91         # array of Register Reservation vectors
  92         # ---
  93         regrsv = Array(Reg_Rsv(self.n_fu_row) for r in range(self.n_reg_col))
  94         for rn in range(self.n_reg_col):
  95             setattr(m.submodules, "rr_r%d" % (rn), regrsv[rn])
  96
  97         # ---
  98         # connect Function Unit vector
  99         # ---
 100         wr_pend = []
 101         rd_pend = []
 102         for fu in range(self.n_fu_row):
 103             dc = dm[fu]
 104             fup = fupend[fu]
 105             dest_fwd_o = []
 106             for rn in range(self.n_reg_col):
 107                 # accumulate cell fwd outputs for dest/src1/src2
 108                 dest_fwd_o.append(dc.dest_fwd_o[rn])
 109             # connect cell fwd outputs to FU Vector in [Cat is gooood]
 110             m.d.comb += [fup.dest_fwd_i.eq(Cat(*dest_fwd_o)),
 111                         ]
 112             # accumulate FU Vector outputs
 113             wr_pend.append(fup.reg_wr_pend_o)
 114             rd_pend.append(fup.reg_rd_pend_o)
 115
 116         # ... and output them from this module (vertical, width=FUs)
 117         m.d.comb += self.wr_pend_o.eq(Cat(*wr_pend))
 118         m.d.comb += self.rd_pend_o.eq(Cat(*rd_pend))
 119
 120         for i in range(self.n_src):
 121             rd_src_pend = []
 122             for fu in range(self.n_fu_row):
 123                 dc = dm[fu]
 124                 fup = fupend[fu]
 125                 src_fwd_o = []
 126                 for rn in range(self.n_reg_col):
 127                     # accumulate cell fwd outputs for dest/src1/src2
 128                     src_fwd_o.append(dc.src_fwd_o[i][rn])
 129                 # connect cell fwd outputs to FU Vector in [Cat is gooood]
 130                 m.d.comb += [fup.src_fwd_i[i].eq(Cat(*src_fwd_o)),
 131                             ]
 132                 # accumulate FU Vector outputs
 133                 rd_src_pend.append(fup.reg_rd_src_pend_o[i])
 134             # ... and output them from this module (vertical, width=FUs)
 135             m.d.comb += self.rd_src_pend_o[i].eq(Cat(*rd_src_pend))
 136
 137         # ---
 138         # connect Reg Selection vector
 139         # ---
 140         dest_rsel = []
 141         src1_rsel = []
 142         src2_rsel = []
 143         for rn in range(self.n_reg_col):
 144             rsv = regrsv[rn]
 145             dest_rsel_o = []
 146             src1_rsel_o = []
 147             src2_rsel_o = []
 148             for fu in range(self.n_fu_row):
 149                 dc = dm[fu]
 150                 # accumulate cell reg-select outputs dest/src1/src2
 151                 dest_rsel_o.append(dc.dest_rsel_o[rn])
 152                 src1_rsel_o.append(dc.src_rsel_o[0][rn])
 153                 src2_rsel_o.append(dc.src_rsel_o[1][rn])
 154             # connect cell reg-select outputs to Reg Vector In
 155             m.d.comb += [rsv.dest_rsel_i.eq(Cat(*dest_rsel_o)),
 156                          rsv.src1_rsel_i.eq(Cat(*src1_rsel_o)),
 157                          rsv.src2_rsel_i.eq(Cat(*src2_rsel_o)),
 158                         ]
 159             # accumulate Reg-Sel Vector outputs
 160             dest_rsel.append(rsv.dest_rsel_o)
 161             src1_rsel.append(rsv.src1_rsel_o)
 162             src2_rsel.append(rsv.src2_rsel_o)
 163
 164         # ... and output them from this module (horizontal, width=REGs)
 165         m.d.comb += self.dest_rsel_o.eq(Cat(*dest_rsel))
 166         m.d.comb += self.src_rsel_o[0].eq(Cat(*src1_rsel))
 167         m.d.comb += self.src_rsel_o[1].eq(Cat(*src2_rsel))
 168
 169         # ---
 170         # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
 171         # ---
 172         for fu in range(self.n_fu_row):
 173             dc = dm[fu]
 174             # wire up inputs from module to row cell inputs (Cat is gooood)
 175             m.d.comb += [dc.dest_i.eq(self.dest_i),
 176                          dc.src_i[0].eq(self.src_i[0]),
 177                          dc.src_i[1].eq(self.src_i[1]),
 178                          dc.rd_pend_i.eq(self.rd_pend_i),
 179                          dc.wr_pend_i.eq(self.wr_pend_i),
 180                         ]
 181
 182         # accumulate rsel bits into read/write pending vectors.
 183         rd_pend_v = []
 184         wr_pend_v = []
 185         for fu in range(self.n_fu_row):
 186             dc = dm[fu]
 187             rd_pend_v.append(dc.v_rd_rsel_o)
 188             wr_pend_v.append(dc.v_wr_rsel_o)
 189         rd_v = GlobalPending(self.n_reg_col, rd_pend_v)
 190         wr_v = GlobalPending(self.n_reg_col, wr_pend_v)
 191         m.submodules.rd_v = rd_v
 192         m.submodules.wr_v = wr_v
 193
 194         m.d.comb += self.v_rd_rsel_o.eq(rd_v.g_pend_o)
 195         m.d.comb += self.v_wr_rsel_o.eq(wr_v.g_pend_o)
 196
 197         # ---
 198         # connect Dep issue_i/go_rd_i/go_wr_i to module issue_i/go_rd/go_wr
 199         # ---
 200         go_rd_i = []
 201         go_wr_i = []
 202         go_die_i = []
 203         issue_i = []
 204         for fu in range(self.n_fu_row):
 205             dc = dm[fu]
 206             # accumulate cell fwd outputs for dest/src1/src2
 207             go_rd_i.append(dc.go_rd_i)
 208             go_wr_i.append(dc.go_wr_i)
 209             go_die_i.append(dc.go_die_i)
 210             issue_i.append(dc.issue_i)
 211         # wire up inputs from module to row cell inputs (Cat is gooood)
 212         m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i),
 213                      Cat(*go_wr_i).eq(self.go_wr_i),
 214                      Cat(*go_die_i).eq(self.go_die_i),
 215                      Cat(*issue_i).eq(self.issue_i),
 216                     ]
 217
 218         return m
 219
 220     def __iter__(self):
 221         yield self.dest_i
 222         yield from self.src_i
 223         yield self.issue_i
 224         yield self.go_wr_i
 225         yield self.go_rd_i
 226         yield self.go_die_i
 227         yield self.dest_rsel_o
 228         yield from self.src_rsel_o
 229         yield self.wr_pend_o
 230         yield self.rd_pend_o
 231         yield self.wr_pend_i
 232         yield self.rd_pend_i
 233         yield self.v_wr_rsel_o
 234         yield self.v_rd_rsel_o
 235         yield from self.rd_src_pend_o
 236
 237     def ports(self):
 238         return list(self)
 239
 240 def d_matrix_sim(dut):
 241     """ XXX TODO
 242     """
 243     yield dut.dest_i.eq(1)
 244     yield dut.issue_i.eq(1)
 245     yield
 246     yield dut.issue_i.eq(0)
 247     yield
 248     yield dut.src1_i.eq(1)
 249     yield dut.issue_i.eq(1)
 250     yield
 251     yield dut.issue_i.eq(0)
 252     yield
 253     yield dut.go_rd_i.eq(1)
 254     yield
 255     yield dut.go_rd_i.eq(0)
 256     yield
 257     yield dut.go_wr_i.eq(1)
 258     yield
 259     yield dut.go_wr_i.eq(0)
 260     yield
 261
 262 def test_d_matrix():
 263     dut = FURegDepMatrix(n_fu_row=3, n_reg_col=4, n_src=2)
 264     vl = rtlil.convert(dut, ports=dut.ports())
 265     with open("test_fu_reg_matrix.il", "w") as f:
 266         f.write(vl)
 267
 268     run_simulation(dut, d_matrix_sim(dut), vcd_name='test_fu_reg_matrix.vcd')
 269
 270 if __name__ == '__main__':
 271     test_d_matrix()