src/scoreboard/fu_wr_pending.py

   1 from nmigen import Elaboratable, Module, Signal, Cat
   2
   3
   4 class FU_RW_Pend(Elaboratable):
   5     """ these are allocated per-FU (horizontally),
   6         and are of length reg_count
   7     """
   8     def __init__(self, reg_count):
   9         self.reg_count = reg_count
  10         self.dest_fwd_i = Signal(reg_count, reset_less=True)
  11         self.src1_fwd_i = Signal(reg_count, reset_less=True)
  12         self.src2_fwd_i = Signal(reg_count, reset_less=True)
  13
  14         self.reg_wr_pend_o = Signal(reset_less=True)
  15         self.reg_rd_pend_o = Signal(reset_less=True)
  16         self.reg_rd_src1_pend_o = Signal(reset_less=True)
  17         self.reg_rd_src2_pend_o = Signal(reset_less=True)
  18
  19     def elaborate(self, platform):
  20         m = Module()
  21         m.d.comb += self.reg_wr_pend_o.eq(self.dest_fwd_i.bool())
  22         m.d.comb += self.reg_rd_src1_pend_o.eq(self.src1_fwd_i.bool())
  23         m.d.comb += self.reg_rd_src2_pend_o.eq(self.src2_fwd_i.bool())
  24         m.d.comb += self.reg_rd_pend_o.eq(self.reg_rd_src1_pend_o |
  25                                           self.reg_rd_src2_pend_o)
  26         return m
  27